Overall: 653/4236 fields covered

ADC

0x40012400: Analog to digital convertor

1/82 fields covered. Toggle Registers.

ISR

ADC interrupt and status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCRDY
rw 		EOCAL
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle Fields.

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

EOCAL

Bit 11: EOCAL.

CCRDY

Bit 13: CCRDY.

IER

ADC interrupt enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCRDYIE
rw 		EOCALIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle Fields.

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

EOCALIE

Bit 11: EOCALIE.

CCRDYIE

Bit 13: CCRDYIE.

CR

ADC control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSTP
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle Fields.

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

ADSTP

Bit 4: ADSTP.

ADVREGEN

Bit 28: ADVREGEN.

ADCAL

Bit 31: ADCAL.

CFGR1

ADC configuration register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD1CH
rw 		AWD1EN
rw 		AWD1SGL
rw 		CHSELRMOD
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTOFF
rw 		WAIT
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		SCANDIR
rw 		DMACFG
rw 		DMAEN
rw
Toggle Fields.

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

SCANDIR

Bit 2: SCANDIR.

RES

Bits 3-4: RES.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-8: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

WAIT

Bit 14: WAIT.

AUTOFF

Bit 15: AUTOFF.

DISCEN

Bit 16: DISCEN.

CHSELRMOD

Bit 21: CHSELRMOD.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

AWD1CH

Bits 26-30: AWD1CH.

CFGR2

ADC configuration register 2

Offset: 0x10, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMODE
rw 		LFTRIG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOVS
rw 		OVSS3
rw 		OVSS2
rw 		OVSS1
rw 		OVSS0
rw 		OVSR2
rw 		OVSR1
rw 		OVSR0
rw 		OVSE
rw
Toggle Fields.

OVSE

Bit 0: OVSE.

OVSR0

Bit 2: OVSR0.

OVSR1

Bit 3: OVSR1.

OVSR2

Bit 4: OVSR2.

OVSS0

Bit 5: OVSS0.

OVSS1

Bit 6: OVSS1.

OVSS2

Bit 7: OVSS2.

OVSS3

Bit 8: OVSS3.

TOVS

Bit 9: TOVS.

LFTRIG

Bit 29: LFTRIG.

CKMODE

Bits 30-31: CKMODE.

SMPR

ADC sampling time register

Offset: 0x14, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSEL
rw 		SMP2
rw 		SMP1
rw
Toggle Fields.

SMP1

Bits 0-2: SMP1.

SMP2

Bits 4-6: SMP2.

SMPSEL

Bits 8-25: SMPSEL.

AWD1TR

ADC watchdog threshold register

Offset: 0x20, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle Fields.

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

AWD2TR

ADC watchdog threshold register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle Fields.

LT2

Bits 0-11: LT2.

HT2

Bits 16-27: HT2.

CHSELR1

channel selection register

Offset: 0x28, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ8
rw 		SQ7
rw 		SQ6
rw 		SQ5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw 		SQ3
rw 		SQ2
rw 		SQ1
rw
Toggle Fields.

SQ1

Bits 0-3: SQ1.

SQ2

Bits 4-7: SQ2.

SQ3

Bits 8-11: SQ3.

SQ4

Bits 12-15: SQ4.

SQ5

Bits 16-19: SQ5.

SQ6

Bits 20-23: SQ6.

SQ7

Bits 24-27: SQ7.

SQ8

Bits 28-31: SQ8.

AWD3TR

ADC watchdog threshold register

Offset: 0x2C, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle Fields.

LT3

Bits 0-11: LT3.

HT3

Bits 16-27: HT3.

DR

ADC data register

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields.

DATA

Bits 0-15: DATA.

AWD2CR

ADC Analog Watchdog 2 Configuration register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle Fields.

AWD2CH

Bits 0-17: AWD2CH.

AWD3CR

ADC Analog Watchdog 3 Configuration register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle Fields.

AWD3CH

Bits 0-17: AWD3CH.

CALFACT

ADC Calibration factor

Offset: 0xB4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT
rw
Toggle Fields.

CALFACT

Bits 0-6: CALFACT.

CCR

ADC common configuration register

Offset: 0x308, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBATEN
rw 		TSEN
rw 		VREFEN
rw 		PRESC3
rw 		PRESC2
rw 		PRESC1
rw 		PRESC0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRESC0

Bit 18: PRESC0.

PRESC1

Bit 19: PRESC1.

PRESC2

Bit 20: PRESC2.

PRESC3

Bit 21: PRESC3.

VREFEN

Bit 22: VREFEN.

TSEN

Bit 23: TSEN.

VBATEN

Bit 24: VBATEN.

AES

0x58001800: Advanced encryption standard hardware accelerator 1

5/40 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPBLB
rw 		KEYSIZE
rw 		CHMOD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GCMPH
rw 		DMAOUTEN
rw 		DMAINEN
rw 		ERRIE
rw 		CCFIE
rw 		ERRC
rw 		CCFC
rw 		CHMOD10
rw 		MODE
rw 		DATATYPE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: AES enable.

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

MODE

Bits 3-4: AES operating mode.

CHMOD10

Bits 5-6: AES chaining mode Bit1 Bit0.

CCFC

Bit 7: Computation Complete Flag Clear.

ERRC

Bit 8: Error clear.

CCFIE

Bit 9: CCF flag interrupt enable.

ERRIE

Bit 10: Error interrupt enable.

DMAINEN

Bit 11: Enable DMA management of data input phase.

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

GCMPH

Bits 13-14: Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected.

CHMOD2

Bit 16: AES chaining mode Bit2.

KEYSIZE

Bit 18: Key size selection.

NPBLB

Bits 20-23: Number of padding bytes in last block of payload.

SR

status register

Offset: 0x4, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		WRERR
r 		RDERR
r 		CCF
r
Toggle Fields.

CCF

Bit 0: Computation complete flag.

RDERR

Bit 1: Read error flag.

WRERR

Bit 2: Write error flag.

BUSY

Bit 3: Busy flag.

DINR

data input register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_DINR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_DINR
rw
Toggle Fields.

AES_DINR

Bits 0-31: Data Input Register.

DOUTR

data output register

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_DOUTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_DOUTR
r
Toggle Fields.

AES_DOUTR

Bits 0-31: Data output register.

KEYR0

key register 0

Offset: 0x10, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR0
w
Toggle Fields.

AES_KEYR0

Bits 0-31: Data Output Register (LSB key [31:0]).

KEYR1

key register 1

Offset: 0x14, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR1
w
Toggle Fields.

AES_KEYR1

Bits 0-31: AES key register (key [63:32]).

KEYR2

key register 2

Offset: 0x18, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR2
w
Toggle Fields.

AES_KEYR2

Bits 0-31: AES key register (key [95:64]).

KEYR3

key register 3

Offset: 0x1C, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR3
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR3
w
Toggle Fields.

AES_KEYR3

Bits 0-31: AES key register (MSB key [127:96]).

IVR0

initialization vector register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR0
rw
Toggle Fields.

AES_IVR0

Bits 0-31: initialization vector register (LSB IVR [31:0]).

IVR1

initialization vector register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR1
rw
Toggle Fields.

AES_IVR1

Bits 0-31: Initialization Vector Register (IVR [63:32]).

IVR2

initialization vector register 2

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR2
rw
Toggle Fields.

AES_IVR2

Bits 0-31: Initialization Vector Register (IVR [95:64]).

IVR3

initialization vector register 3

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR3
rw
Toggle Fields.

AES_IVR3

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

KEYR4

key register 4

Offset: 0x30, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR4
w
Toggle Fields.

AES_KEYR4

Bits 0-31: AES key register (MSB key [159:128]).

KEYR5

key register 5

Offset: 0x34, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR5
w
Toggle Fields.

AES_KEYR5

Bits 0-31: AES key register (MSB key [191:160]).

KEYR6

key register 6

Offset: 0x38, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR6
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR6
w
Toggle Fields.

AES_KEYR6

Bits 0-31: AES key register (MSB key [223:192]).

KEYR7

key register 7

Offset: 0x3C, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR7
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR7
w
Toggle Fields.

AES_KEYR7

Bits 0-31: AES key register (MSB key [255:224]).

SUSP0R

AES suspend register 0

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_SUSP0R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_SUSP0R
rw
Toggle Fields.

AES_SUSP0R

Bits 0-31: AES suspend register 0.

SUSP1R

AES suspend register 1

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_SUSP1R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_SUSP1R
rw
Toggle Fields.

AES_SUSP1R

Bits 0-31: AES suspend register 1.

SUSP2R

AES suspend register 2

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_SUSP2R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_SUSP2R
rw
Toggle Fields.

AES_SUSP2R

Bits 0-31: AES suspend register 2.

SUSP3R

AES suspend register 3

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_SUSP3R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_SUSP3R
rw
Toggle Fields.

AES_SUSP3R

Bits 0-31: AES suspend register 3.

SUSP4R

AES suspend register 4

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_SUSP4R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_SUSP4R
rw
Toggle Fields.

AES_SUSP4R

Bits 0-31: AES suspend register 4.

SUSP5R

AES suspend register 5

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_SUSP5R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_SUSP5R
rw
Toggle Fields.

AES_SUSP5R

Bits 0-31: AES suspend register 5.

SUSP6R

AES suspend register 6

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_SUSP6R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_SUSP6R
rw
Toggle Fields.

AES_SUSP6R

Bits 0-31: AES suspend register 6.

SUSP7R

AES suspend register 7

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_SUSP7R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_SUSP7R
rw
Toggle Fields.

AES_SUSP7R

Bits 0-31: AES suspend register 7.

COMP

0x40010200: Comparator

2/25 fields covered. Toggle Registers.

COMP1_CSR

COMP1_CSR

Offset: 0x0, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		VALUE
r 		INMESEL
rw 		SCALEN
rw 		BRGEN
rw 		BLANKING
rw 		HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLARITY
rw 		INPSEL
rw 		INMSEL
rw 		PWRMODE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: Comparator 1 enable bit.

PWRMODE

Bits 2-3: Power Mode of the comparator 1.

INMSEL

Bits 4-6: Comparator 1 input minus selection bits.

INPSEL

Bits 7-8: Comparator1 input plus selection bit.

POLARITY

Bit 15: Comparator 1 polarity selection bit.

HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

BLANKING

Bits 18-20: Comparator 1 blanking source selection bits.

BRGEN

Bit 22: Scaler bridge enable.

SCALEN

Bit 23: Voltage scaler enable bit.

INMESEL

Bits 25-26: comparator 1 input minus extended selection bits..

VALUE

Bit 30: Comparator 1 output status bit.

LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

COMP2_CSR

Offset: 0x4, reset: 0x00000000, access: Unspecified

1/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		VALUE
r 		INMESEL
rw 		SCALEN
rw 		BRGEN
rw 		BLANKING
rw 		HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLARITY
rw 		WINMODE
rw 		INPSEL
rw 		INMSEL
rw 		PWRMODE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: Comparator 2 enable bit.

PWRMODE

Bits 2-3: Power Mode of the comparator 2.

INMSEL

Bits 4-6: Comparator 2 input minus selection bits.

INPSEL

Bits 7-8: Comparator 1 input plus selection bit.

WINMODE

Bit 9: Windows mode selection bit.

POLARITY

Bit 15: Comparator 2 polarity selection bit.

HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

BRGEN

Bit 22: Scaler bridge enable.

SCALEN

Bit 23: Voltage scaler enable bit.

INMESEL

Bits 25-26: comparator 2 input minus extended selection bits..

VALUE

Bit 30: Comparator 2 output status bit.

LOCK

Bit 31: CSR register lock bit.

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered. Toggle Registers.

DR

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle Fields.

IDR

Bits 0-31: General-purpose 32-bit data register bits.

CR

Control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
rw
Toggle Fields.

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle Fields.

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle Fields.

POL

Bits 0-31: Programmable polynomial.

DAC

0x40007400: Digital-to-analog converter

3/27 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEN1
rw 		DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL13
rw 		TSEL12
rw 		TSEL11
rw 		TSEL10
rw 		TEN1
rw 		EN1
rw
Toggle Fields.

EN1

Bit 0: DAC channel1 enable.

TEN1

Bit 1: DAC channel1 trigger enable.

TSEL10

Bit 2: TSEL10.

TSEL11

Bit 3: TSEL11.

TSEL12

Bit 4: TSEL12.

TSEL13

Bit 5: DAC channel1 trigger selection.

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

DMAEN1

Bit 12: DAC channel1 DMA enable.

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

CEN1

Bit 14: DAC Channel 1 calibration enable.

SWTRGR

software trigger register

Offset: 0x4, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG1
w
Toggle Fields.

SWTRIG1

Bit 0: DAC channel1 software trigger.

DHR12R1

channel1 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DHR12L1

channel1 12-bit left aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DHR8R1

channel1 8-bit right aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DHR12LD

Dual DAC 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DHR8RD

Dual DAC 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DOR1

DAC channel1 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle Fields.

DACC1DOR

Bits 0-11: DACC1DOR.

SR

status register

Offset: 0x34, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST1
r 		CAL_FLAG1
r 		DMAUDR1
rw
Toggle Fields.

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

CAL_FLAG1

Bit 14: DAC Channel 1 calibration offset status.

BWST1

Bit 15: DAC Channel 1 busy writing sample time flag.

CCR

calibration control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM1
rw
Toggle Fields.

OTRIM1

Bits 0-4: DAC Channel 1 offset trimming value.

MCR

mode control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE1
rw
Toggle Fields.

MODE1

Bits 0-2: DAC Channel 1 mode.

SHSR1

Sample and Hold sample time register 1

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE1
rw
Toggle Fields.

TSAMPLE1

Bits 0-9: DAC Channel 1 sample Time (only valid in Sample and Hold mode).

SHHR

Sample and Hold hold time register

Offset: 0x48, reset: 0x00010001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD1
rw
Toggle Fields.

THOLD1

Bits 0-9: DAC Channel 1 hold Time (only valid in Sample and Hold mode).

SHRR

Sample and Hold refresh time register

Offset: 0x4C, reset: 0x00010001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH1
rw
Toggle Fields.

TREFRESH1

Bits 0-7: DAC Channel 1 refresh Time (only valid in Sample and Hold mode).

DBGMCU

0xE0042000: Microcontroller Debug Unit

2/30 fields covered. Toggle Registers.

IDCODER

DBGMCU Identity Code Register

Offset: 0x0, reset: 0x10006497, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle Fields.

DEV_ID

Bits 0-11: Device ID.

REV_ID

Bits 16-31: Revision.

CR

DBGMCU Configuration Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_STANDBY
rw 		DBG_STOP
rw 		DBG_SLEEP
rw
Toggle Fields.

DBG_SLEEP

Bit 0: Allow debug in SLEEP mode.

DBG_STOP

Bit 1: Allow debug in STOP mode.

DBG_STANDBY

Bit 2: Allow debug in STANDBY mode.

APB1FZR1

DBGMCU CPU1 APB1 Peripheral Freeze Register 1

Offset: 0x3C, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIM1_STOP
rw 		DBG_I2C3_STOP
rw 		DBG_I2C2_STOP
rw 		DBG_I2C1_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw 		DBG_WWDG_STOP
rw 		DBG_RTC_STOP
rw 		DBG_TIM2_STOP
rw
Toggle Fields.

DBG_TIM2_STOP

Bit 0: TIM2 stop in CPU1 debug.

DBG_RTC_STOP

Bit 10: RTC stop in CPU1 debug.

DBG_WWDG_STOP

Bit 11: WWDG stop in CPU1 debug.

DBG_IWDG_STOP

Bit 12: IWDG stop in CPU1 debug.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout stop in CPU1 debug.

DBG_I2C2_STOP

Bit 22: I2C2 SMBUS timeout stop in CPU1 debug.

DBG_I2C3_STOP

Bit 23: I2C3 SMBUS timeout stop in CPU1 debug.

DBG_LPTIM1_STOP

Bit 31: LPTIM1 stop in CPU1 debug.

C2APB1FZR1

DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device

Offset: 0x40, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIM1_STOP
rw 		DBG_I2C3_STOP
rw 		DBG_I2C2_STOP
rw 		DBG_I2C1_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw 		DBG_RTC_STOP
rw 		DBG_TIM2_STOP
rw
Toggle Fields.

DBG_TIM2_STOP

Bit 0: DBG_TIM2_STOP.

DBG_RTC_STOP

Bit 10: DBG_RTC_STOP.

DBG_IWDG_STOP

Bit 12: DBG_IWDG_STOP.

DBG_I2C1_STOP

Bit 21: DBG_I2C1_STOP.

DBG_I2C2_STOP

Bit 22: DBG_I2C2_STOP.

DBG_I2C3_STOP

Bit 23: DBG_I2C3_STOP.

DBG_LPTIM1_STOP

Bit 31: DBG_LPTIM1_STOP.

APB1FZR2

DBGMCU CPU1 APB1 Peripheral Freeze Register 2

Offset: 0x44, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_LPTIM3_STOP
rw 		DBG_LPTIM2_STOP
rw
Toggle Fields.

DBG_LPTIM2_STOP

Bit 5: DBG_LPTIM2_STOP.

DBG_LPTIM3_STOP

Bit 6: DBG_LPTIM3_STOP.

C2APB1FZR2

DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device

Offset: 0x48, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_LPTIM3_STOP
rw 		DBG_LPTIM2_STOP
rw
Toggle Fields.

DBG_LPTIM2_STOP

Bit 5: DBG_LPTIM2_STOP.

DBG_LPTIM3_STOP

Bit 6: DBG_LPTIM3_STOP.

APB2FZR

DBGMCU CPU1 APB2 Peripheral Freeze Register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM17_STOP
rw 		DBG_TIM16_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM1_STOP
rw
Toggle Fields.

DBG_TIM1_STOP

Bit 11: DBG_TIM1_STOP.

DBG_TIM16_STOP

Bit 17: DBG_TIM16_STOP.

DBG_TIM17_STOP

Bit 18: DBG_TIM17_STOP.

C2APB2FZR

DBGMCU CPU2 APB2 Peripheral Freeze Register [dual core device

Offset: 0x50, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM17_STOP
rw 		DBG_TIM16_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM1_STOP
rw
Toggle Fields.

DBG_TIM1_STOP

Bit 11: DBG_TIM1_STOP.

DBG_TIM16_STOP

Bit 17: DBG_TIM16_STOP.

DBG_TIM17_STOP

Bit 18: DBG_TIM17_STOP.

DMA1

0x40020000: Direct memory access controller

28/189 fields covered. Toggle Registers.

ISR

interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle Fields.

GIF1

Bit 0: global interrupt flag for channel 1.

TCIF1

Bit 1: transfer complete (TC) flag for channel 1.

HTIF1

Bit 2: half transfer (HT) flag for channel 1.

TEIF1

Bit 3: transfer error (TE) flag for channel 1.

GIF2

Bit 4: global interrupt flag for channel 2.

TCIF2

Bit 5: transfer complete (TC) flag for channel 2.

HTIF2

Bit 6: half transfer (HT) flag for channel 2.

TEIF2

Bit 7: transfer error (TE) flag for channel 2.

GIF3

Bit 8: global interrupt flag for channel 3.

TCIF3

Bit 9: transfer complete (TC) flag for channel 3.

HTIF3

Bit 10: half transfer (HT) flag for channel 3.

TEIF3

Bit 11: transfer error (TE) flag for channel 3.

GIF4

Bit 12: global interrupt flag for channel 4.

TCIF4

Bit 13: transfer complete (TC) flag for channel 4.

HTIF4

Bit 14: half transfer (HT) flag for channel 4.

TEIF4

Bit 15: transfer error (TE) flag for channel 4.

GIF5

Bit 16: global interrupt flag for channel 5.

TCIF5

Bit 17: transfer complete (TC) flag for channel 5.

HTIF5

Bit 18: half transfer (HT) flag for channel 5.

TEIF5

Bit 19: transfer error (TE) flag for channel 5.

GIF6

Bit 20: global interrupt flag for channel 6.

TCIF6

Bit 21: transfer complete (TC) flag for channel 6.

HTIF6

Bit 22: half transfer (HT) flag for channel 6.

TEIF6

Bit 23: transfer error (TE) flag for channel 6.

GIF7

Bit 24: global interrupt flag for channel 7.

TCIF7

Bit 25: transfer complete (TC) flag for channel 7.

HTIF7

Bit 26: half transfer (HT) flag for channel 7.

TEIF7

Bit 27: transfer error (TE) flag for channel 7.

IFCR

interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
w 		HTIF7
w 		TCIF7
w 		GIF7
w 		TEIF6
w 		HTIF6
w 		TCIF6
w 		GIF6
w 		TEIF5
w 		HTIF5
w 		TCIF5
w 		GIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
w 		HTIF4
w 		TCIF4
w 		GIF4
w 		TEIF3
w 		HTIF3
w 		TCIF3
w 		GIF3
w 		TEIF2
w 		HTIF2
w 		TCIF2
w 		GIF2
w 		TEIF1
w 		HTIF1
w 		TCIF1
w 		GIF1
w
Toggle Fields.

GIF1

Bit 0: global interrupt flag clear for channel 1.

TCIF1

Bit 1: transfer complete flag clear for channel 1.

HTIF1

Bit 2: half transfer flag clear for channel 1.

TEIF1

Bit 3: transfer error flag clear for channel 1.

GIF2

Bit 4: global interrupt flag clear for channel 2.

TCIF2

Bit 5: transfer complete flag clear for channel 2.

HTIF2

Bit 6: half transfer flag clear for channel 2.

TEIF2

Bit 7: transfer error flag clear for channel 2.

GIF3

Bit 8: global interrupt flag clear for channel 3.

TCIF3

Bit 9: transfer complete flag clear for channel 3.

HTIF3

Bit 10: half transfer flag clear for channel 3.

TEIF3

Bit 11: transfer error flag clear for channel 3.

GIF4

Bit 12: global interrupt flag clear for channel 4.

TCIF4

Bit 13: transfer complete flag clear for channel 4.

HTIF4

Bit 14: half transfer flag clear for channel 4.

TEIF4

Bit 15: transfer error flag clear for channel 4.

GIF5

Bit 16: global interrupt flag clear for channel 5.

TCIF5

Bit 17: transfer complete flag clear for channel 5.

HTIF5

Bit 18: half transfer flag clear for channel 5.

TEIF5

Bit 19: transfer error flag clear for channel 5.

GIF6

Bit 20: global interrupt flag clear for channel 6.

TCIF6

Bit 21: transfer complete flag clear for channel 6.

HTIF6

Bit 22: half transfer flag clear for channel 6.

TEIF6

Bit 23: transfer error flag clear for channel 6.

GIF7

Bit 24: global interrupt flag clear for channel 7.

TCIF7

Bit 25: transfer complete flag clear for channel 7.

HTIF7

Bit 26: half transfer flag clear for channel 7.

TEIF7

Bit 27: transfer error flag clear for channel 7.

CCR1

channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR1

channel x number of data to transfer register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR1

channel x peripheral address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR2

channel x configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR2

channel x number of data to transfer register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR2

channel x peripheral address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR3

channel x configuration register

Offset: 0x30, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR3

channel x number of data to transfer register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR3

channel x peripheral address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR3

channel x memory address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR4

channel x configuration register

Offset: 0x44, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR4

channel x number of data to transfer register

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR4

channel x peripheral address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR5

channel x configuration register

Offset: 0x58, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR5

channel x number of data to transfer register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR5

channel x peripheral address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR6

channel x configuration register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR6

channel x number of data to transfer register

Offset: 0x70, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR6

channel x peripheral address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR7

channel x configuration register

Offset: 0x80, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR7

channel x number of data to transfer register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR7

channel x peripheral address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR7

channel x memory address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

DMA2

0x40020400: Direct memory access controller

28/189 fields covered. Toggle Registers.

ISR

interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle Fields.

GIF1

Bit 0: global interrupt flag for channel 1.

TCIF1

Bit 1: transfer complete (TC) flag for channel 1.

HTIF1

Bit 2: half transfer (HT) flag for channel 1.

TEIF1

Bit 3: transfer error (TE) flag for channel 1.

GIF2

Bit 4: global interrupt flag for channel 2.

TCIF2

Bit 5: transfer complete (TC) flag for channel 2.

HTIF2

Bit 6: half transfer (HT) flag for channel 2.

TEIF2

Bit 7: transfer error (TE) flag for channel 2.

GIF3

Bit 8: global interrupt flag for channel 3.

TCIF3

Bit 9: transfer complete (TC) flag for channel 3.

HTIF3

Bit 10: half transfer (HT) flag for channel 3.

TEIF3

Bit 11: transfer error (TE) flag for channel 3.

GIF4

Bit 12: global interrupt flag for channel 4.

TCIF4

Bit 13: transfer complete (TC) flag for channel 4.

HTIF4

Bit 14: half transfer (HT) flag for channel 4.

TEIF4

Bit 15: transfer error (TE) flag for channel 4.

GIF5

Bit 16: global interrupt flag for channel 5.

TCIF5

Bit 17: transfer complete (TC) flag for channel 5.

HTIF5

Bit 18: half transfer (HT) flag for channel 5.

TEIF5

Bit 19: transfer error (TE) flag for channel 5.

GIF6

Bit 20: global interrupt flag for channel 6.

TCIF6

Bit 21: transfer complete (TC) flag for channel 6.

HTIF6

Bit 22: half transfer (HT) flag for channel 6.

TEIF6

Bit 23: transfer error (TE) flag for channel 6.

GIF7

Bit 24: global interrupt flag for channel 7.

TCIF7

Bit 25: transfer complete (TC) flag for channel 7.

HTIF7

Bit 26: half transfer (HT) flag for channel 7.

TEIF7

Bit 27: transfer error (TE) flag for channel 7.

IFCR

interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
w 		HTIF7
w 		TCIF7
w 		GIF7
w 		TEIF6
w 		HTIF6
w 		TCIF6
w 		GIF6
w 		TEIF5
w 		HTIF5
w 		TCIF5
w 		GIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
w 		HTIF4
w 		TCIF4
w 		GIF4
w 		TEIF3
w 		HTIF3
w 		TCIF3
w 		GIF3
w 		TEIF2
w 		HTIF2
w 		TCIF2
w 		GIF2
w 		TEIF1
w 		HTIF1
w 		TCIF1
w 		GIF1
w
Toggle Fields.

GIF1

Bit 0: global interrupt flag clear for channel 1.

TCIF1

Bit 1: transfer complete flag clear for channel 1.

HTIF1

Bit 2: half transfer flag clear for channel 1.

TEIF1

Bit 3: transfer error flag clear for channel 1.

GIF2

Bit 4: global interrupt flag clear for channel 2.

TCIF2

Bit 5: transfer complete flag clear for channel 2.

HTIF2

Bit 6: half transfer flag clear for channel 2.

TEIF2

Bit 7: transfer error flag clear for channel 2.

GIF3

Bit 8: global interrupt flag clear for channel 3.

TCIF3

Bit 9: transfer complete flag clear for channel 3.

HTIF3

Bit 10: half transfer flag clear for channel 3.

TEIF3

Bit 11: transfer error flag clear for channel 3.

GIF4

Bit 12: global interrupt flag clear for channel 4.

TCIF4

Bit 13: transfer complete flag clear for channel 4.

HTIF4

Bit 14: half transfer flag clear for channel 4.

TEIF4

Bit 15: transfer error flag clear for channel 4.

GIF5

Bit 16: global interrupt flag clear for channel 5.

TCIF5

Bit 17: transfer complete flag clear for channel 5.

HTIF5

Bit 18: half transfer flag clear for channel 5.

TEIF5

Bit 19: transfer error flag clear for channel 5.

GIF6

Bit 20: global interrupt flag clear for channel 6.

TCIF6

Bit 21: transfer complete flag clear for channel 6.

HTIF6

Bit 22: half transfer flag clear for channel 6.

TEIF6

Bit 23: transfer error flag clear for channel 6.

GIF7

Bit 24: global interrupt flag clear for channel 7.

TCIF7

Bit 25: transfer complete flag clear for channel 7.

HTIF7

Bit 26: half transfer flag clear for channel 7.

TEIF7

Bit 27: transfer error flag clear for channel 7.

CCR1

channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR1

channel x number of data to transfer register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR1

channel x peripheral address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR2

channel x configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR2

channel x number of data to transfer register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR2

channel x peripheral address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR3

channel x configuration register

Offset: 0x30, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR3

channel x number of data to transfer register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR3

channel x peripheral address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR3

channel x memory address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR4

channel x configuration register

Offset: 0x44, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR4

channel x number of data to transfer register

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR4

channel x peripheral address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR5

channel x configuration register

Offset: 0x58, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR5

channel x number of data to transfer register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR5

channel x peripheral address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR6

channel x configuration register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR6

channel x number of data to transfer register

Offset: 0x70, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR6

channel x peripheral address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

CCR7

channel x configuration register

Offset: 0x80, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle Fields.

EN

Bit 0: channel enable.

TCIE

Bit 1: transfer complete interrupt enable.

HTIE

Bit 2: half transfer interrupt enable.

TEIE

Bit 3: transfer error interrupt enable.

DIR

Bit 4: data transfer direction.

CIRC

Bit 5: circular mode.

PINC

Bit 6: peripheral increment mode.

MINC

Bit 7: memory increment mode.

PSIZE

Bits 8-9: peripheral size.

MSIZE

Bits 10-11: memory size.

PL

Bits 12-13: priority level.

MEM2MEM

Bit 14: memory-to-memory mode.

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

CNDTR7

channel x number of data to transfer register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

CPAR7

channel x peripheral address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: peripheral address.

CMAR7

channel x memory address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: peripheral address.

DMAMUX

0x40020800: DMA request multiplexer

18/154 fields covered. Toggle Registers.

C0CR

request line multiplexer channel x configuration register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C1CR

request line multiplexer channel x configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C2CR

request line multiplexer channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C3CR

request line multiplexer channel x configuration register

Offset: 0xC, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C4CR

request line multiplexer channel x configuration register

Offset: 0x10, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C5CR

request line multiplexer channel x configuration register

Offset: 0x14, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C6CR

request line multiplexer channel x configuration register

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C7CR

request line multiplexer channel x configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C8CR

request line multiplexer channel x configuration register

Offset: 0x20, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C9CR

request line multiplexer channel x configuration register

Offset: 0x24, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

C10CR

C10CR

Offset: 0x28, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-28: SYNC_ID.

C11CR

C11CR

Offset: 0x2C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-28: SYNC_ID.

C12CR

C12CR

Offset: 0x30, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-28: SYNC_ID.

C13CR

C13CR

Offset: 0x34, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-7: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-28: SYNC_ID.

CSR

request line multiplexer interrupt channel status register

Offset: 0x80, reset: 0x00000000, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF13
r 		SOF12
r 		SOF11
r 		SOF10
r 		SOF9
r 		SOF8
r 		SOF7
r 		SOF6
r 		SOF5
r 		SOF4
r 		SOF3
r 		SOF2
r 		SOF1
r 		SOF0
r
Toggle Fields.

SOF0

Bit 0: SOF0.

SOF1

Bit 1: SOF1.

SOF2

Bit 2: SOF2.

SOF3

Bit 3: SOF3.

SOF4

Bit 4: SOF4.

SOF5

Bit 5: SOF5.

SOF6

Bit 6: SOF6.

SOF7

Bit 7: SOF7.

SOF8

Bit 8: SOF8.

SOF9

Bit 9: SOF9.

SOF10

Bit 10: SOF10.

SOF11

Bit 11: SOF11.

SOF12

Bit 12: SOF12.

SOF13

Bit 13: Synchronization overrun event flag.

CCFR

request line multiplexer interrupt channel clear flag register

Offset: 0x84, reset: 0x00000000, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF13
w 		CSOF12
w 		CSOF11
w 		CSOF10
w 		CSOF9
w 		CSOF8
w 		CSOF7
w 		CSOF6
w 		CSOF5
w 		CSOF4
w 		CSOF3
w 		CSOF2
w 		CSOF1
w 		CSOF0
w
Toggle Fields.

CSOF0

Bit 0: CSOF0.

CSOF1

Bit 1: CSOF1.

CSOF2

Bit 2: CSOF2.

CSOF3

Bit 3: CSOF3.

CSOF4

Bit 4: CSOF4.

CSOF5

Bit 5: CSOF5.

CSOF6

Bit 6: CSOF6.

CSOF7

Bit 7: CSOF7.

CSOF8

Bit 8: CSOF8.

CSOF9

Bit 9: CSOF9.

CSOF10

Bit 10: CSOF10.

CSOF11

Bit 11: CSOF11.

CSOF12

Bit 12: CSOF12.

CSOF13

Bit 13: CSOF13.

RG0CR

request generator channel x configuration register

Offset: 0x100, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle Fields.

SIG_ID

Bits 0-4: Signal identification.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1).

RG1CR

request generator channel x configuration register

Offset: 0x104, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle Fields.

SIG_ID

Bits 0-4: Signal identification.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1).

RG2CR

request generator channel x configuration register

Offset: 0x108, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle Fields.

SIG_ID

Bits 0-4: Signal identification.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1).

RG3CR

request generator channel x configuration register

Offset: 0x10C, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle Fields.

SIG_ID

Bits 0-4: Signal identification.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1).

RGSR

request generator interrupt status register

Offset: 0x140, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF3
r 		OF2
r 		OF1
r 		OF0
r
Toggle Fields.

OF0

Bit 0: OF0.

OF1

Bit 1: OF1.

OF2

Bit 2: OF2.

OF3

Bit 3: Trigger overrun event flag.

RGCFR

request generator interrupt clear flag register

Offset: 0x144, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF3
w 		COF2
w 		COF1
w 		COF0
w
Toggle Fields.

COF0

Bit 0: COF0.

COF1

Bit 1: COF1.

COF2

Bit 2: COF2.

COF3

Bit 3: Clear trigger overrun event flag.

EXTI

0x58000800: External interrupt/event controller

0/98 fields covered. Toggle Registers.

RTSR1

rising trigger selection register

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT21
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-16: Rising trigger event configuration bit of Configurable Event input.

RT21

Bits 21-22: Rising trigger event configuration bit of Configurable Event input.

FTSR1

falling trigger selection register

Offset: 0x4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FT21
rw 		FT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT
rw
Toggle Fields.

FT

Bits 0-16: Falling trigger event configuration bit of Configurable Event input.

FT21

Bits 21-22: Falling trigger event configuration bit of Configurable Event input.

SWIER1

software interrupt event register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI21
rw 		SWI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI
rw
Toggle Fields.

SWI

Bits 0-16: Software interrupt on event.

SWI21

Bits 21-22: Software interrupt on event.

PR1

EXTI pending register

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIF21
rw 		PIF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIF
rw
Toggle Fields.

PIF

Bits 0-16: Configurable event inputs Pending bit.

PIF21

Bits 21-22: Configurable event inputs Pending bit.

RTSR2

rising trigger selection register

Offset: 0x20, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT45
rw 		RT41
rw 		RT40
rw 		RT34
rw
Toggle Fields.

RT34

Bit 2: Rising trigger event configuration bit of Configurable Event input.

RT40

Bit 8: Rising trigger event configuration bit of Configurable Event input.

RT41

Bit 9: Rising trigger event configuration bit of Configurable Event input.

RT45

Bit 13: Rising trigger event configuration bit of Configurable Event input.

FTSR2

falling trigger selection register

Offset: 0x24, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT45
rw 		FT41
rw 		FT40
rw 		FT34
rw
Toggle Fields.

FT34

Bit 2: Falling trigger event configuration bit of Configurable Event input.

FT40

Bit 8: Falling trigger event configuration bit of Configurable Event input.

FT41

Bit 9: Falling trigger event configuration bit of Configurable Event input.

FT45

Bit 13: Falling trigger event configuration bit of Configurable Event input.

SWIER2

software interrupt event register

Offset: 0x28, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI45
rw 		SWI41
rw 		SWI40
rw 		SWI34
rw
Toggle Fields.

SWI34

Bit 2: Software interrupt on event.

SWI40

Bit 8: Software interrupt on event.

SWI41

Bit 9: Software interrupt on event.

SWI45

Bit 13: Software interrupt on event 45.

PR2

pending register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIF45
rw 		PIF41
rw 		PIF40
rw 		PIF34
rw
Toggle Fields.

PIF34

Bit 2: Configurable event inputs 33 Pending bit..

PIF40

Bit 8: Configurable event inputs 40_41 Pending bit..

PIF41

Bit 9: Configurable event inputs 40_41 Pending bit..

PIF45

Bit 13: Configurable event inputs 45 Pending bit..

C1IMR1

interrupt mask register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM
rw
Toggle Fields.

IM

Bits 0-31: wakeup with interrupt Mask on event input.

C1EMR1

event mask register

Offset: 0x84, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM22
rw 		EM21
rw 		EM20
rw 		EM19
rw 		EM18
rw 		EM17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw 		EM14
rw 		EM13
rw 		EM12
rw 		EM11
rw 		EM10
rw 		EM9
rw 		EM8
rw 		EM7
rw 		EM6
rw 		EM5
rw 		EM4
rw 		EM3
rw 		EM2
rw 		EM1
rw 		EM0
rw
Toggle Fields.

EM0

Bit 0: Wakeup with event generation Mask on Event input.

EM1

Bit 1: Wakeup with event generation Mask on Event input.

EM2

Bit 2: Wakeup with event generation Mask on Event input.

EM3

Bit 3: Wakeup with event generation Mask on Event input.

EM4

Bit 4: Wakeup with event generation Mask on Event input.

EM5

Bit 5: Wakeup with event generation Mask on Event input.

EM6

Bit 6: Wakeup with event generation Mask on Event input.

EM7

Bit 7: Wakeup with event generation Mask on Event input.

EM8

Bit 8: Wakeup with event generation Mask on Event input.

EM9

Bit 9: Wakeup with event generation Mask on Event input.

EM10

Bit 10: Wakeup with event generation Mask on Event input.

EM11

Bit 11: Wakeup with event generation Mask on Event input.

EM12

Bit 12: Wakeup with event generation Mask on Event input.

EM13

Bit 13: Wakeup with event generation Mask on Event input.

EM14

Bit 14: Wakeup with event generation Mask on Event input.

EM15

Bit 15: Wakeup with event generation Mask on Event input.

EM17

Bit 17: Wakeup with event generation Mask on Event input.

EM18

Bit 18: Wakeup with event generation Mask on Event input.

EM19

Bit 19: Wakeup with event generation Mask on Event input.

EM20

Bit 20: Wakeup with event generation Mask on Event input.

EM21

Bit 21: Wakeup with event generation Mask on Event input.

EM22

Bit 22: Wakeup with event generation Mask on Event input.

C1IMR2

wakeup with interrupt mask register

Offset: 0x90, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM46
rw 		IM45
rw 		IM44
rw 		IM43
rw 		IM42
rw 		IM41
rw 		IM40
rw 		IM39
rw 		IM38
rw 		IM37
rw 		IM36
rw 		IM34
rw
Toggle Fields.

IM34

Bit 2: wakeup with interrupt mask on event input.

IM36

Bit 4: wakeup with interrupt mask on event input.

IM37

Bit 5: wakeup with interrupt mask on event input.

IM38

Bit 6: wakeup with interrupt mask on event input.

IM39

Bit 7: wakeup with interrupt mask on event input.

IM40

Bit 8: wakeup with interrupt mask on event input.

IM41

Bit 9: wakeup with interrupt mask on event input.

IM42

Bit 10: wakeup with interrupt mask on event input.

IM43

Bit 11: wakeup with interrupt mask on event input.

IM44

Bit 12: wakeup with interrupt mask on event input.

IM45

Bit 13: wakeup with interrupt mask on event input.

IM46

Bit 14: wakeup with interrupt mask on event input.

C1EMR2

wakeup with event mask register

Offset: 0x94, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM41
rw 		EM40
rw
Toggle Fields.

EM40

Bit 8: Wakeup with event generation Mask on Event input.

EM41

Bit 9: Wakeup with event generation Mask on Event input.

C2IMR1

interrupt mask register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM
rw
Toggle Fields.

IM

Bits 0-31: wakeup with interrupt Mask on Event input.

C2EMR1

event mask register

Offset: 0xC4, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM22
rw 		EM21
rw 		EM20
rw 		EM19
rw 		EM18
rw 		EM17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw 		EM14
rw 		EM13
rw 		EM12
rw 		EM11
rw 		EM10
rw 		EM9
rw 		EM8
rw 		EM7
rw 		EM6
rw 		EM5
rw 		EM4
rw 		EM3
rw 		EM2
rw 		EM1
rw 		EM0
rw
Toggle Fields.

EM0

Bit 0: Wakeup with event generation Mask on Event input.

EM1

Bit 1: Wakeup with event generation Mask on Event input.

EM2

Bit 2: Wakeup with event generation Mask on Event input.

EM3

Bit 3: Wakeup with event generation Mask on Event input.

EM4

Bit 4: Wakeup with event generation Mask on Event input.

EM5

Bit 5: Wakeup with event generation Mask on Event input.

EM6

Bit 6: Wakeup with event generation Mask on Event input.

EM7

Bit 7: Wakeup with event generation Mask on Event input.

EM8

Bit 8: Wakeup with event generation Mask on Event input.

EM9

Bit 9: Wakeup with event generation Mask on Event input.

EM10

Bit 10: Wakeup with event generation Mask on Event input.

EM11

Bit 11: Wakeup with event generation Mask on Event input.

EM12

Bit 12: Wakeup with event generation Mask on Event input.

EM13

Bit 13: Wakeup with event generation Mask on Event input.

EM14

Bit 14: Wakeup with event generation Mask on Event input.

EM15

Bit 15: Wakeup with event generation Mask on Event input.

EM17

Bit 17: Wakeup with event generation Mask on Event input.

EM18

Bit 18: Wakeup with event generation Mask on Event input.

EM19

Bit 19: Wakeup with event generation Mask on Event input.

EM20

Bit 20: Wakeup with event generation Mask on Event input.

EM21

Bit 21: Wakeup with event generation Mask on Event input.

EM22

Bit 22: Wakeup with event generation Mask on Event input.

C2IMR2

wakeup with interrupt mask register

Offset: 0xD0, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM46
rw 		IM45
rw 		IM44
rw 		IM43
rw 		IM42
rw 		IM41
rw 		IM40
rw 		IM39
rw 		IM38
rw 		IM37
rw 		IM36
rw 		IM34
rw
Toggle Fields.

IM34

Bit 2: wakeup with interrupt mask on event input.

IM36

Bit 4: wakeup with interrupt mask on event input.

IM37

Bit 5: wakeup with interrupt mask on event input.

IM38

Bit 6: wakeup with interrupt mask on event input.

IM39

Bit 7: wakeup with interrupt mask on event input.

IM40

Bit 8: wakeup with interrupt mask on event input.

IM41

Bit 9: wakeup with interrupt mask on event input.

IM42

Bit 10: wakeup with interrupt mask on event input.

IM43

Bit 11: wakeup with interrupt mask on event input.

IM44

Bit 12: wakeup with interrupt mask on event input.

IM45

Bit 13: wakeup with interrupt mask on event input.

IM46

Bit 14: wakeup with interrupt mask on event input.

C2EMR2

wakeup with event mask register

Offset: 0xD4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM41
rw 		EM40
rw
Toggle Fields.

EM40

Bit 8: Wakeup with event generation Mask on Event input.

EM41

Bit 9: Wakeup with event generation Mask on Event input.

FLASH

0x58004000: Flash

10/112 fields covered. Toggle Registers.

ACR

Access control register

Offset: 0x0, reset: 0x00000600, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EMPTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PES
rw 		DCRST
rw 		ICRST
rw 		DCEN
rw 		ICEN
rw 		PRFTEN
rw 		LATENCY
rw
Toggle Fields.

LATENCY

Bits 0-2: Latency.

PRFTEN

Bit 8: Prefetch enable.

ICEN

Bit 9: Instruction cache enable.

DCEN

Bit 10: Data cache enable.

ICRST

Bit 11: Instruction cache reset.

DCRST

Bit 12: Data cache reset.

PES

Bit 15: CPU1 programm erase suspend request.

EMPTY

Bit 16: Flash User area empty.

ACR2

Flash access control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2SWDBGEN
rw 		HDPADIS
rw 		PRIVMODE
rw
Toggle Fields.

PRIVMODE

Bit 0: CFI privileged mode enable.

HDPADIS

Bit 1: Flash user hide protection area access disable.

C2SWDBGEN

Bit 2: CPU2 Software debug enable.

KEYR

Flash key register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: KEY.

OPTKEYR

Option byte key register

Offset: 0xC, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEY
w
Toggle Fields.

OPTKEY

Bits 0-31: Option byte key.

SR

Status register

Offset: 0x10, reset: 0x00000000, access: Unspecified

4/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PESD
r 		CFGBSY
r 		BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR
rw 		RDERR
rw 		OPTVN
r 		FASTERR
rw 		MISERR
rw 		PGSERR
rw 		SIZERR
rw 		PGAERR
rw 		WRPERR
rw 		PROGERR
rw 		OPERR
rw 		EOP
rw
Toggle Fields.

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: Write protected error.

PGAERR

Bit 5: Programming alignment error.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

OPTVN

Bit 13: User Option OPTIVAL indication.

RDERR

Bit 14: PCROP read error.

OPTVERR

Bit 15: Option validity error.

BSY

Bit 16: Busy.

CFGBSY

Bit 18: Programming or erase configuration busy.

PESD

Bit 19: Programming / erase operation suspended.

CR

Flash control register

Offset: 0x14, reset: 0xC0000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		OPTLOCK
rw 		OBL_LAUNCH
rw 		RDERRIE
rw 		ERRIE
rw 		EOPIE
rw 		FSTPG
rw 		OPTSTRT
rw 		STRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PNB
rw 		MER
rw 		PER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER

Bit 2: Mass erase.

PNB

Bits 3-9: Page number.

STRT

Bit 16: Start.

OPTSTRT

Bit 17: Options modification start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: PCROP read error interrupt enable.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

LOCK

Bit 31: FLASH_CR Lock.

ECCR

Flash ECC register

Offset: 0x18, reset: 0x00000000, access: Unspecified

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD
rw 		ECCC
rw 		CPUID
r 		ECCCIE
rw 		SYSF_ECC
r 		ADDR_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC
r
Toggle Fields.

ADDR_ECC

Bits 0-16: ECC fail address.

SYSF_ECC

Bit 20: System Flash ECC fail.

ECCCIE

Bit 24: ECC correction interrupt enable.

CPUID

Bits 26-28: CPU identification.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x20, reset: 0x3FFFF0AA, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C2BOOT_LOCK
rw 		BOOT_LOCK
rw 		nBOOT0
rw 		nSWBOOT0
rw 		SRAM2_RST
rw 		SRAM2_PE
rw 		nBOOT1
rw 		WWDG_SW
rw 		IWDG_STDBY
rw 		IWDG_STOP
rw 		IWDG_SW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_SHDW
rw 		nRST_STDBY
rw 		nRST_STOP
rw 		BOR_LEV
rw 		ESE
rw 		RDP
rw
Toggle Fields.

RDP

Bits 0-7: Read protection level.

ESE

Bit 8: System security enabled flag.

BOR_LEV

Bits 9-11: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

nRST_SHDW

Bit 14: nRSTSHDW.

IWDG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

nBOOT1

Bit 23: Boot configuration.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: Software BOOT0 selection.

nBOOT0

Bit 27: nBOOT0 option bit.

BOOT_LOCK

Bit 30: CPU1 CM4 Unique Boot entry enable option bit.

C2BOOT_LOCK

Bit 31: CPU2 CM0+ Unique Boot entry enable option bit.

PCROP1ASR

Flash PCROP zone A Start address register

Offset: 0x24, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1A_STRT
rw
Toggle Fields.

PCROP1A_STRT

Bits 0-7: PCROP1A area start offset.

PCROP1AER

Flash PCROP zone A End address register

Offset: 0x28, reset: 0xFFFFFF00, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCROP_RDP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1A_END
rw
Toggle Fields.

PCROP1A_END

Bits 0-7: PCROP area end offset.

PCROP_RDP

Bit 31: PCROP area preserved when RDP level decreased.

WRP1AR

Flash WRP area A address register

Offset: 0x2C, reset: 0xFF80FFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1A_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1A_STRT
rw
Toggle Fields.

WRP1A_STRT

Bits 0-6: Bank 1 WRP first area start offset.

WRP1A_END

Bits 16-22: Bank 1 WRP first area A end offset.

WRP1BR

Flash WRP area B address register

Offset: 0x30, reset: 0xFF80FFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1B_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1B_STRT
rw
Toggle Fields.

WRP1B_STRT

Bits 0-6: Bank 1 WRP second area B end offset.

WRP1B_END

Bits 16-22: Bank 1 WRP second area B start offset.

PCROP1BSR

Flash PCROP zone B Start address register

Offset: 0x34, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1B_STRT
rw
Toggle Fields.

PCROP1B_STRT

Bits 0-7: Bank 1 WRP second area B end offset.

PCROP1BER

Flash PCROP zone B End address register

Offset: 0x38, reset: 0xFFFFFF00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1B_END
rw
Toggle Fields.

PCROP1B_END

Bits 0-7: PCROP1B area end offset.

IPCCBR

Flash IPCC data buffer address register

Offset: 0x3C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCDBA
rw
Toggle Fields.

IPCCDBA

Bits 0-13: IPCCDBA.

C2ACR

Flash CPU2 access control register

Offset: 0x5C, reset: 0x00000600, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PES
rw 		ICRST
rw 		ICEN
rw 		PRFTEN
rw
Toggle Fields.

PRFTEN

Bit 8: CPU2 Prefetch enable.

ICEN

Bit 9: CPU2 Instruction cache enable.

ICRST

Bit 11: CPU2 Instruction cache reset.

PES

Bit 15: CPU2 program / erase suspend request.

C2SR

Flash CPU2 status register

Offset: 0x60, reset: 0x00000000, access: Unspecified

3/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PESD
r 		CFGBSY
r 		BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDERR
rw 		FASTERR
rw 		MISERR
rw 		PGSERR
rw 		SIZERR
rw 		PGAERR
rw 		WRPERR
rw 		PROGERR
rw 		OPERR
rw 		EOP
rw
Toggle Fields.

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: WRPERR.

PGAERR

Bit 5: PGAERR.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

RDERR

Bit 14: PCROP read error.

BSY

Bit 16: BSY.

CFGBSY

Bit 18: CFGBSY.

PESD

Bit 19: PESD.

C2CR

Flash CPU2 control register

Offset: 0x64, reset: 0xC0000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDERRIE
rw 		ERRIE
rw 		EOPIE
rw 		FSTPG
rw 		STRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PNB
rw 		MER
rw 		PER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER

Bit 2: Mass erase.

PNB

Bits 3-9: Page number selection.

STRT

Bit 16: Start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: RDERRIE.

SFR

Flash secure Flash start address register

Offset: 0x80, reset: 0xFFFFEFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUBGHSPISD
rw 		HDPAD
rw 		HDPSA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDS
rw 		FSD
rw 		SFSA
rw
Toggle Fields.

SFSA

Bits 0-6: Secure Flash start address.

FSD

Bit 7: Flash security disabled.

DDS

Bit 12: DDS.

HDPSA

Bits 16-22: User Flash hide protection area start address.

HDPAD

Bit 23: User Flash hide protection area disabled.

SUBGHSPISD

Bit 31: sub-GHz radio SPI security disable.

SRRVR

Flash secure SRAM start address and CPU2 reset vector register

Offset: 0x84, reset: 0xFFFF8000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C2OPT
rw 		NBRSD
rw 		SNBRSA
rw 		BRSD
rw 		SBRSA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBRV
rw
Toggle Fields.

SBRV

Bits 0-15: CPU2 boot reset vector.

SBRSA

Bits 18-22: Secure backup SRAM2 start address.

BRSD

Bit 23: backup SRAM2 security disable.

SNBRSA

Bits 25-29: Secure non-backup SRAM1 start address.

NBRSD

Bit 30: NBRSD.

C2OPT

Bit 31: C2OPT.

GPIOA

0x48000000: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xABFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x0C000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x64000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

GPIO port bit reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
rw 		BR14
rw 		BR13
rw 		BR12
rw 		BR11
rw 		BR10
rw 		BR9
rw 		BR8
rw 		BR7
rw 		BR6
rw 		BR5
rw 		BR4
rw 		BR3
rw 		BR2
rw 		BR1
rw 		BR0
rw
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOB

0x48000400: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFEBF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x000000C0, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000100, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

GPIO port bit reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
rw 		BR14
rw 		BR13
rw 		BR12
rw 		BR11
rw 		BR10
rw 		BR9
rw 		BR8
rw 		BR7
rw 		BR6
rw 		BR5
rw 		BR4
rw 		BR3
rw 		BR2
rw 		BR1
rw 		BR0
rw
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOC

0x48000800: General-purpose I/Os

10/117 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFC003FFF, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

GPIO port bit reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
rw 		BR14
rw 		BR13
rw 		BR6
rw 		BR5
rw 		BR4
rw 		BR3
rw 		BR2
rw 		BR1
rw 		BR0
rw
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOH

0x48001C00: General-purpose I/Os

1/20 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x000000C0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER3
rw
Toggle Fields.

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT3
rw
Toggle Fields.

OT3

Bit 3: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR3
rw
Toggle Fields.

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR3
rw
Toggle Fields.

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR3
r
Toggle Fields.

IDR3

Bit 3: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR3
rw
Toggle Fields.

ODR3

Bit 3: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR3
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS3
w
Toggle Fields.

BS3

Bit 3: Port x set bit y (y= 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK3
rw
Toggle Fields.

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
Toggle Fields.

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

GPIO port bit reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR3
rw
Toggle Fields.

BR3

Bit 3: Port Reset bit.

HSEM

0x58001400: Hardware semaphore

128/227 fields covered. Toggle Registers.

HSEM_R0

HSEM register HSEM_R0 HSEM_R31

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R1

HSEM register HSEM_R0 HSEM_R31

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R2

HSEM register HSEM_R0 HSEM_R31

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R3

HSEM register HSEM_R0 HSEM_R31

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R4

HSEM register HSEM_R0 HSEM_R31

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R5

HSEM register HSEM_R0 HSEM_R31

Offset: 0x14, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R6

HSEM register HSEM_R0 HSEM_R31

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R7

HSEM register HSEM_R0 HSEM_R31

Offset: 0x1C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R8

HSEM register HSEM_R0 HSEM_R31

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R9

HSEM register HSEM_R0 HSEM_R31

Offset: 0x24, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R10

HSEM register HSEM_R0 HSEM_R31

Offset: 0x28, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R11

HSEM register HSEM_R0 HSEM_R31

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R12

HSEM register HSEM_R0 HSEM_R31

Offset: 0x30, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R13

HSEM register HSEM_R0 HSEM_R31

Offset: 0x34, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R14

HSEM register HSEM_R0 HSEM_R31

Offset: 0x38, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_R15

HSEM register HSEM_R0 HSEM_R31

Offset: 0x3C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR0

HSEM Read lock register

Offset: 0x80, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR1

HSEM Read lock register

Offset: 0x84, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR2

HSEM Read lock register

Offset: 0x88, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR3

HSEM Read lock register

Offset: 0x8C, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR4

HSEM Read lock register

Offset: 0x90, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR5

HSEM Read lock register

Offset: 0x94, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR6

HSEM Read lock register

Offset: 0x98, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR7

HSEM Read lock register

Offset: 0x9C, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR8

HSEM Read lock register

Offset: 0xA0, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR9

HSEM Read lock register

Offset: 0xA4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR10

HSEM Read lock register

Offset: 0xA8, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR11

HSEM Read lock register

Offset: 0xAC, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR12

HSEM Read lock register

Offset: 0xB0, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR13

HSEM Read lock register

Offset: 0xB4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR14

HSEM Read lock register

Offset: 0xB8, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_RLR15

HSEM Read lock register

Offset: 0xBC, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: Lock indication.

HSEM_C1IER

HSEM Interrupt enable register

Offset: 0x100, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISE15
rw 		ISE14
rw 		ISE13
rw 		ISE12
rw 		ISE11
rw 		ISE10
rw 		ISE9
rw 		ISE8
rw 		ISE7
rw 		ISE6
rw 		ISE5
rw 		ISE4
rw 		ISE3
rw 		ISE2
rw 		ISE1
rw 		ISE0
rw
Toggle Fields.

ISE0

Bit 0: Interrupt semaphore n enable bit.

ISE1

Bit 1: Interrupt semaphore n enable bit.

ISE2

Bit 2: Interrupt semaphore n enable bit.

ISE3

Bit 3: Interrupt semaphore n enable bit.

ISE4

Bit 4: Interrupt semaphore n enable bit.

ISE5

Bit 5: Interrupt semaphore n enable bit.

ISE6

Bit 6: Interrupt semaphore n enable bit.

ISE7

Bit 7: Interrupt semaphore n enable bit.

ISE8

Bit 8: Interrupt semaphore n enable bit.

ISE9

Bit 9: Interrupt semaphore n enable bit.

ISE10

Bit 10: Interrupt semaphore n enable bit.

ISE11

Bit 11: Interrupt semaphore n enable bit.

ISE12

Bit 12: Interrupt semaphore n enable bit.

ISE13

Bit 13: Interrupt semaphore n enable bit.

ISE14

Bit 14: Interrupt semaphore n enable bit.

ISE15

Bit 15: Interrupt semaphore n enable bit.

HSEM_C1ICR

HSEM Interrupt clear register

Offset: 0x104, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISC15
rw 		ISC14
rw 		ISC13
rw 		ISC12
rw 		ISC11
rw 		ISC10
rw 		ISC9
rw 		ISC8
rw 		ISC7
rw 		ISC6
rw 		ISC5
rw 		ISC4
rw 		ISC3
rw 		ISC2
rw 		ISC1
rw 		ISC0
rw
Toggle Fields.

ISC0

Bit 0: Interrupt(N) semaphore n clear bit.

ISC1

Bit 1: Interrupt(N) semaphore n clear bit.

ISC2

Bit 2: Interrupt(N) semaphore n clear bit.

ISC3

Bit 3: Interrupt(N) semaphore n clear bit.

ISC4

Bit 4: Interrupt(N) semaphore n clear bit.

ISC5

Bit 5: Interrupt(N) semaphore n clear bit.

ISC6

Bit 6: Interrupt(N) semaphore n clear bit.

ISC7

Bit 7: Interrupt(N) semaphore n clear bit.

ISC8

Bit 8: Interrupt(N) semaphore n clear bit.

ISC9

Bit 9: Interrupt(N) semaphore n clear bit.

ISC10

Bit 10: Interrupt(N) semaphore n clear bit.

ISC11

Bit 11: Interrupt(N) semaphore n clear bit.

ISC12

Bit 12: Interrupt(N) semaphore n clear bit.

ISC13

Bit 13: Interrupt(N) semaphore n clear bit.

ISC14

Bit 14: Interrupt(N) semaphore n clear bit.

ISC15

Bit 15: Interrupt(N) semaphore n clear bit.

HSEM_C1ISR

HSEM Interrupt status register

Offset: 0x108, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISF15
r 		ISF14
r 		ISF13
r 		ISF12
r 		ISF11
r 		ISF10
r 		ISF9
r 		ISF8
r 		ISF7
r 		ISF6
r 		ISF5
r 		ISF4
r 		ISF3
r 		ISF2
r 		ISF1
r 		ISF0
r
Toggle Fields.

ISF0

Bit 0: Interrupt(N) semaphore n status bit before enable (mask).

ISF1

Bit 1: Interrupt(N) semaphore n status bit before enable (mask).

ISF2

Bit 2: Interrupt(N) semaphore n status bit before enable (mask).

ISF3

Bit 3: Interrupt(N) semaphore n status bit before enable (mask).

ISF4

Bit 4: Interrupt(N) semaphore n status bit before enable (mask).

ISF5

Bit 5: Interrupt(N) semaphore n status bit before enable (mask).

ISF6

Bit 6: Interrupt(N) semaphore n status bit before enable (mask).

ISF7

Bit 7: Interrupt(N) semaphore n status bit before enable (mask).

ISF8

Bit 8: Interrupt(N) semaphore n status bit before enable (mask).

ISF9

Bit 9: Interrupt(N) semaphore n status bit before enable (mask).

ISF10

Bit 10: Interrupt(N) semaphore n status bit before enable (mask).

ISF11

Bit 11: Interrupt(N) semaphore n status bit before enable (mask).

ISF12

Bit 12: Interrupt(N) semaphore n status bit before enable (mask).

ISF13

Bit 13: Interrupt(N) semaphore n status bit before enable (mask).

ISF14

Bit 14: Interrupt(N) semaphore n status bit before enable (mask).

ISF15

Bit 15: Interrupt(N) semaphore n status bit before enable (mask).

HSEM_C1MISR

HSEM Masked interrupt status register

Offset: 0x10C, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISF15
r 		MISF14
r 		MISF13
r 		MISF12
r 		MISF11
r 		MISF10
r 		MISF9
r 		MISF8
r 		MISF7
r 		MISF6
r 		MISF5
r 		MISF4
r 		MISF3
r 		MISF2
r 		MISF1
r 		MISF0
r
Toggle Fields.

MISF0

Bit 0: masked interrupt(N) semaphore n status bit after enable (mask).

MISF1

Bit 1: masked interrupt(N) semaphore n status bit after enable (mask).

MISF2

Bit 2: masked interrupt(N) semaphore n status bit after enable (mask).

MISF3

Bit 3: masked interrupt(N) semaphore n status bit after enable (mask).

MISF4

Bit 4: masked interrupt(N) semaphore n status bit after enable (mask).

MISF5

Bit 5: masked interrupt(N) semaphore n status bit after enable (mask).

MISF6

Bit 6: masked interrupt(N) semaphore n status bit after enable (mask).

MISF7

Bit 7: masked interrupt(N) semaphore n status bit after enable (mask).

MISF8

Bit 8: masked interrupt(N) semaphore n status bit after enable (mask).

MISF9

Bit 9: masked interrupt(N) semaphore n status bit after enable (mask).

MISF10

Bit 10: masked interrupt(N) semaphore n status bit after enable (mask).

MISF11

Bit 11: masked interrupt(N) semaphore n status bit after enable (mask).

MISF12

Bit 12: masked interrupt(N) semaphore n status bit after enable (mask).

MISF13

Bit 13: masked interrupt(N) semaphore n status bit after enable (mask).

MISF14

Bit 14: masked interrupt(N) semaphore n status bit after enable (mask).

MISF15

Bit 15: masked interrupt(N) semaphore n status bit after enable (mask).

HSEM_C2IER

HSEM Interrupt enable register

Offset: 0x110, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISE15
rw 		ISE14
rw 		ISE13
rw 		ISE12
rw 		ISE11
rw 		ISE10
rw 		ISE9
rw 		ISE8
rw 		ISE7
rw 		ISE6
rw 		ISE5
rw 		ISE4
rw 		ISE3
rw 		ISE2
rw 		ISE1
rw 		ISE0
rw
Toggle Fields.

ISE0

Bit 0: Interrupt semaphore n enable bit.

ISE1

Bit 1: Interrupt semaphore n enable bit.

ISE2

Bit 2: Interrupt semaphore n enable bit.

ISE3

Bit 3: Interrupt semaphore n enable bit.

ISE4

Bit 4: Interrupt semaphore n enable bit.

ISE5

Bit 5: Interrupt semaphore n enable bit.

ISE6

Bit 6: Interrupt semaphore n enable bit.

ISE7

Bit 7: Interrupt semaphore n enable bit.

ISE8

Bit 8: Interrupt semaphore n enable bit.

ISE9

Bit 9: Interrupt semaphore n enable bit.

ISE10

Bit 10: Interrupt semaphore n enable bit.

ISE11

Bit 11: Interrupt semaphore n enable bit.

ISE12

Bit 12: Interrupt semaphore n enable bit.

ISE13

Bit 13: Interrupt semaphore n enable bit.

ISE14

Bit 14: Interrupt semaphore n enable bit.

ISE15

Bit 15: Interrupt semaphore n enable bit.

HSEM_C2ICR

HSEM Interrupt clear register

Offset: 0x114, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISC15
r 		ISC14
r 		ISC13
r 		ISC12
r 		ISC11
r 		ISC10
r 		ISC9
r 		ISC8
r 		ISC7
r 		ISC6
r 		ISC5
r 		ISC4
r 		ISC3
r 		ISC2
r 		ISC1
r 		ISC0
r
Toggle Fields.

ISC0

Bit 0: Interrupt(N) semaphore n clear bit.

ISC1

Bit 1: Interrupt(N) semaphore n clear bit.

ISC2

Bit 2: Interrupt(N) semaphore n clear bit.

ISC3

Bit 3: Interrupt(N) semaphore n clear bit.

ISC4

Bit 4: Interrupt(N) semaphore n clear bit.

ISC5

Bit 5: Interrupt(N) semaphore n clear bit.

ISC6

Bit 6: Interrupt(N) semaphore n clear bit.

ISC7

Bit 7: Interrupt(N) semaphore n clear bit.

ISC8

Bit 8: Interrupt(N) semaphore n clear bit.

ISC9

Bit 9: Interrupt(N) semaphore n clear bit.

ISC10

Bit 10: Interrupt(N) semaphore n clear bit.

ISC11

Bit 11: Interrupt(N) semaphore n clear bit.

ISC12

Bit 12: Interrupt(N) semaphore n clear bit.

ISC13

Bit 13: Interrupt(N) semaphore n clear bit.

ISC14

Bit 14: Interrupt(N) semaphore n clear bit.

ISC15

Bit 15: Interrupt(N) semaphore n clear bit.

HSEM_C2ISR

HSEM Interrupt status register

Offset: 0x118, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISF15
r 		ISF14
r 		ISF13
r 		ISF12
r 		ISF11
r 		ISF10
r 		ISF9
r 		ISF8
r 		ISF7
r 		ISF6
r 		ISF5
r 		ISF4
r 		ISF3
r 		ISF2
r 		ISF1
r 		ISF0
r
Toggle Fields.

ISF0

Bit 0: Interrupt(N) semaphore n status bit before enable (mask).

ISF1

Bit 1: Interrupt(N) semaphore n status bit before enable (mask).

ISF2

Bit 2: Interrupt(N) semaphore n status bit before enable (mask).

ISF3

Bit 3: Interrupt(N) semaphore n status bit before enable (mask).

ISF4

Bit 4: Interrupt(N) semaphore n status bit before enable (mask).

ISF5

Bit 5: Interrupt(N) semaphore n status bit before enable (mask).

ISF6

Bit 6: Interrupt(N) semaphore n status bit before enable (mask).

ISF7

Bit 7: Interrupt(N) semaphore n status bit before enable (mask).

ISF8

Bit 8: Interrupt(N) semaphore n status bit before enable (mask).

ISF9

Bit 9: Interrupt(N) semaphore n status bit before enable (mask).

ISF10

Bit 10: Interrupt(N) semaphore n status bit before enable (mask).

ISF11

Bit 11: Interrupt(N) semaphore n status bit before enable (mask).

ISF12

Bit 12: Interrupt(N) semaphore n status bit before enable (mask).

ISF13

Bit 13: Interrupt(N) semaphore n status bit before enable (mask).

ISF14

Bit 14: Interrupt(N) semaphore n status bit before enable (mask).

ISF15

Bit 15: Interrupt(N) semaphore n status bit before enable (mask).

HSEM_C2MISR

HSEM Masked interrupt status register

Offset: 0x11C, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISF15
r 		MISF14
r 		MISF13
r 		MISF12
r 		MISF11
r 		MISF10
r 		MISF9
r 		MISF8
r 		MISF7
r 		MISF6
r 		MISF5
r 		MISF4
r 		MISF3
r 		MISF2
r 		MISF1
r 		MISF0
r
Toggle Fields.

MISF0

Bit 0: masked interrupt(N) semaphore n status bit after enable (mask).

MISF1

Bit 1: masked interrupt(N) semaphore n status bit after enable (mask).

MISF2

Bit 2: masked interrupt(N) semaphore n status bit after enable (mask).

MISF3

Bit 3: masked interrupt(N) semaphore n status bit after enable (mask).

MISF4

Bit 4: masked interrupt(N) semaphore n status bit after enable (mask).

MISF5

Bit 5: masked interrupt(N) semaphore n status bit after enable (mask).

MISF6

Bit 6: masked interrupt(N) semaphore n status bit after enable (mask).

MISF7

Bit 7: masked interrupt(N) semaphore n status bit after enable (mask).

MISF8

Bit 8: masked interrupt(N) semaphore n status bit after enable (mask).

MISF9

Bit 9: masked interrupt(N) semaphore n status bit after enable (mask).

MISF10

Bit 10: masked interrupt(N) semaphore n status bit after enable (mask).

MISF11

Bit 11: masked interrupt(N) semaphore n status bit after enable (mask).

MISF12

Bit 12: masked interrupt(N) semaphore n status bit after enable (mask).

MISF13

Bit 13: masked interrupt(N) semaphore n status bit after enable (mask).

MISF14

Bit 14: masked interrupt(N) semaphore n status bit after enable (mask).

MISF15

Bit 15: masked interrupt(N) semaphore n status bit after enable (mask).

HSEM_CR

HSEM Clear register

Offset: 0x140, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
w
Toggle Fields.

COREID

Bits 8-11: COREID.

KEY

Bits 16-31: Semaphore clear Key.

HSEM_KEYR

HSEM Interrupt clear register

Offset: 0x144, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

KEY

Bits 16-31: Semaphore Clear Key.

I2C1

0x40005400: Inter-integrated circuit

17/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

I2C2

0x40005800: Inter-integrated circuit

17/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

I2C3

0x40005C00: Inter-integrated circuit

17/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

IPCC

0x58000C00: Inter Processor communication controller

17/69 fields covered. Toggle Registers.

C1CR

IPCC Processor 1 control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXOIE
rw
Toggle Fields.

RXOIE

Bit 0: RXOIE.

TXFIE

Bit 16: TXFIE.

C1MR

IPCC Processor 1 mask register

Offset: 0x4, reset: 0xFFFFFFFF, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH6FM
rw 		CH5FM
rw 		CH4FM
rw 		CH3FM
rw 		CH2FM
rw 		CH1FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH6OM
rw 		CH5OM
rw 		CH4OM
rw 		CH3OM
rw 		CH2OM
rw 		CH1OM
rw
Toggle Fields.

CH1OM

Bit 0: CH1OM.

CH2OM

Bit 1: CH2OM.

CH3OM

Bit 2: CH3OM.

CH4OM

Bit 3: CH4OM.

CH5OM

Bit 4: CH5OM.

CH6OM

Bit 5: CH6OM.

CH1FM

Bit 16: CH1FM.

CH2FM

Bit 17: CH2FM.

CH3FM

Bit 18: CH3FM.

CH4FM

Bit 19: CH4FM.

CH5FM

Bit 20: CH5FM.

CH6FM

Bit 21: CH6FM.

C1SCR

Reading this register will always return 0x0000 0000.

Offset: 0x8, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH6S
rw 		CH5S
rw 		CH4S
rw 		CH3S
rw 		CH2S
rw 		CH1S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH6C
rw 		CH5C
rw 		CH4C
rw 		CH3C
rw 		CH2C
rw 		CH1C
rw
Toggle Fields.

CH1C

Bit 0: CH1C.

CH2C

Bit 1: CH2C.

CH3C

Bit 2: CH3C.

CH4C

Bit 3: CH4C.

CH5C

Bit 4: CH5C.

CH6C

Bit 5: CH6C.

CH1S

Bit 16: CH1S.

CH2S

Bit 17: CH2S.

CH3S

Bit 18: CH3S.

CH4S

Bit 19: CH4S.

CH5S

Bit 20: CH5S.

CH6S

Bit 21: CH6S.

IC1TOC2SR

IPCC processor 1 to processor 2 status register

Offset: 0xC, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH6F
r 		CH5F
r 		CH4F
r 		CH3F
r 		CH2F
r 		CH1F
r
Toggle Fields.

CH1F

Bit 0: CH1F.

CH2F

Bit 1: CH2F.

CH3F

Bit 2: CH3F.

CH4F

Bit 3: CH4F.

CH5F

Bit 4: CH5F.

CH6F

Bit 5: CH6F.

C2CR

IPCC Processor 2 control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXOIE
rw
Toggle Fields.

RXOIE

Bit 0: RXOIE.

TXFIE

Bit 16: TXFIE.

C2MR

IPCC Processor 2 mask register

Offset: 0x14, reset: 0xFFFFFFFF, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH6FM
rw 		CH5FM
rw 		CH4FM
rw 		CH3FM
rw 		CH2FM
rw 		CH1FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH6OM
rw 		CH5OM
rw 		CH4OM
rw 		CH3OM
rw 		CH2OM
rw 		CH1OM
rw
Toggle Fields.

CH1OM

Bit 0: CH1OM.

CH2OM

Bit 1: CH2OM.

CH3OM

Bit 2: CH3OM.

CH4OM

Bit 3: CH4OM.

CH5OM

Bit 4: CH5OM.

CH6OM

Bit 5: CH6OM.

CH1FM

Bit 16: CH1FM.

CH2FM

Bit 17: CH2FM.

CH3FM

Bit 18: CH3FM.

CH4FM

Bit 19: CH4FM.

CH5FM

Bit 20: CH5FM.

CH6FM

Bit 21: CH6FM.

C2SCR

Reading this register will always return 0x0000 0000.

Offset: 0x18, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH6S
rw 		CH5S
rw 		CH4S
rw 		CH3S
rw 		CH2S
rw 		CH1S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH6C
rw 		CH5C
rw 		CH4C
rw 		CH3C
rw 		CH2C
rw 		CH1C
rw
Toggle Fields.

CH1C

Bit 0: CH1C.

CH2C

Bit 1: CH2C.

CH3C

Bit 2: CH3C.

CH4C

Bit 3: CH4C.

CH5C

Bit 4: CH5C.

CH6C

Bit 5: CH6C.

CH1S

Bit 16: CH1S.

CH2S

Bit 17: CH2S.

CH3S

Bit 18: CH3S.

CH4S

Bit 19: CH4S.

CH5S

Bit 20: CH5S.

CH6S

Bit 21: CH6S.

C2TOC1SR

IPCC processor 2 to processor 1 status register

Offset: 0x1C, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH6F
r 		CH5F
r 		CH4F
r 		CH3F
r 		CH2F
r 		CH1F
r
Toggle Fields.

CH1F

Bit 0: CH1F.

CH2F

Bit 1: CH2F.

CH3F

Bit 2: CH3F.

CH4F

Bit 3: CH4F.

CH5F

Bit 4: CH5F.

CH6F

Bit 5: CH6F.

HWCFGR

IPCC Hardware configuration register

Offset: 0x3F0, reset: 0x00000006, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHANNELS
r
Toggle Fields.

CHANNELS

Bits 0-7: CHANNELS.

VERR

IPCC IP Version register

Offset: 0x3F4, reset: 0x00000010, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle Fields.

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

IPCC IP Identification register

Offset: 0x3F8, reset: 0x00100071, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle Fields.

ID

Bits 0-31: ID.

SIDR

IPCC Size ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle Fields.

SID

Bits 0-31: SID.

IWDG

0x40003000: Independent watchdog

3/7 fields covered. Toggle Registers.

KR

Key register

Offset: 0x0, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, reset: 0x00000007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle Fields.

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle Fields.

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle Fields.

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle Fields.

WIN

Bits 0-11: Watchdog counter window value.

LPTIM1

0x40007C00: Low-power timer

10/51 fields covered. Toggle Registers.

ISR

interrupt and status register

Offset: 0x0, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle Fields.

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

interrupt clear register

Offset: 0x4, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle Fields.

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

interrupt enable register

Offset: 0x8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: Repetition register update OK interrupt Enable.

CFGR

configuration register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle Fields.

CKSEL

Bit 0: CKSEL.

CKPOL

Bits 1-2: CKPOL.

CKFLT

Bits 3-4: CKFLT.

TRGFLT

Bits 6-7: TRGFLT.

PRESC

Bits 9-11: PRESC.

TRIGSEL

Bits 13-15: TRIGSEL.

TRIGEN

Bits 17-18: TRIGEN.

TIMOUT

Bit 19: TIMOUT.

WAVE

Bit 20: WAVE.

WAVPOL

Bit 21: WAVPOL.

PRELOAD

Bit 22: PRELOAD.

COUNTMODE

Bit 23: COUNTMODE.

ENC

Bit 24: ENC.

CR

control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: ENABLE.

SNGSTRT

Bit 1: SNGSTRT.

CNTSTRT

Bit 2: CNTSTRT.

COUNTRST

Bit 3: COUNTRST.

RSTARE

Bit 4: RSTARE.

CMP

compare register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle Fields.

CMP

Bits 0-15: CMP.

ARR

autoreload register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto reload value.

CNT

counter register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields.

CNT

Bits 0-15: Counter value.

LPTIM1_OR

option register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle Fields.

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

repetition register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition register value.

LPTIM2

0x40009400: Low-power timer

10/51 fields covered. Toggle Registers.

ISR

interrupt and status register

Offset: 0x0, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle Fields.

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

interrupt clear register

Offset: 0x4, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle Fields.

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

interrupt enable register

Offset: 0x8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: Repetition register update OK interrupt Enable.

CFGR

configuration register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle Fields.

CKSEL

Bit 0: CKSEL.

CKPOL

Bits 1-2: CKPOL.

CKFLT

Bits 3-4: CKFLT.

TRGFLT

Bits 6-7: TRGFLT.

PRESC

Bits 9-11: PRESC.

TRIGSEL

Bits 13-15: TRIGSEL.

TRIGEN

Bits 17-18: TRIGEN.

TIMOUT

Bit 19: TIMOUT.

WAVE

Bit 20: WAVE.

WAVPOL

Bit 21: WAVPOL.

PRELOAD

Bit 22: PRELOAD.

COUNTMODE

Bit 23: COUNTMODE.

ENC

Bit 24: ENC.

CR

control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: ENABLE.

SNGSTRT

Bit 1: SNGSTRT.

CNTSTRT

Bit 2: CNTSTRT.

COUNTRST

Bit 3: COUNTRST.

RSTARE

Bit 4: RSTARE.

CMP

compare register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle Fields.

CMP

Bits 0-15: CMP.

ARR

autoreload register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto reload value.

CNT

counter register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields.

CNT

Bits 0-15: Counter value.

LPTIM2_OR

option register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle Fields.

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

repetition register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition register value.

LPTIM3

0x40009800: Low-power timer

10/51 fields covered. Toggle Registers.

ISR

interrupt and status register

Offset: 0x0, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle Fields.

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

interrupt clear register

Offset: 0x4, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle Fields.

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

interrupt enable register

Offset: 0x8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: Repetition register update OK interrupt Enable.

CFGR

configuration register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle Fields.

CKSEL

Bit 0: CKSEL.

CKPOL

Bits 1-2: CKPOL.

CKFLT

Bits 3-4: CKFLT.

TRGFLT

Bits 6-7: TRGFLT.

PRESC

Bits 9-11: PRESC.

TRIGSEL

Bits 13-15: TRIGSEL.

TRIGEN

Bits 17-18: TRIGEN.

TIMOUT

Bit 19: TIMOUT.

WAVE

Bit 20: WAVE.

WAVPOL

Bit 21: WAVPOL.

PRELOAD

Bit 22: PRELOAD.

COUNTMODE

Bit 23: COUNTMODE.

ENC

Bit 24: ENC.

CR

control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: ENABLE.

SNGSTRT

Bit 1: SNGSTRT.

CNTSTRT

Bit 2: CNTSTRT.

COUNTRST

Bit 3: COUNTRST.

RSTARE

Bit 4: RSTARE.

CMP

compare register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle Fields.

CMP

Bits 0-15: CMP.

ARR

autoreload register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto reload value.

CNT

counter register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields.

CNT

Bits 0-15: Counter value.

LPTIM3_OR

option register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle Fields.

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

repetition register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition register value.

LPUART

0x40008000: Universal synchronous asynchronous receiver transmitter

39/120 fields covered. Toggle Registers.

CR1_disabled

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw 		M1
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXFNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields.

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: Transmit data register empty.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		STOP
rw 		ADDM7
rw
Toggle Fields.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

STOP

Bits 12-13: STOP bits.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ADD

Bits 24-31: Address of the LPUART node.

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		HDSEL
rw 		EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

HDSEL

Bit 3: Half-duplex selection.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-19: BRR.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w
Toggle Fields.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt and status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r 		CTSIF
r 		TXE
r 		TC
r 		RXFNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TCCF

Bit 6: Transmission complete clear flag.

CTSCF

Bit 9: CTS clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler.

MPU

0xE000ED90: Memory protection unit

6/19 fields covered. Toggle Registers.

MPU_TYPER

MPU type register

Offset: 0x0, reset: 0X00000800, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREGION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DREGION
r 		SEPARATE
r
Toggle Fields.

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

MPU_CTRL

MPU control register

Offset: 0x4, reset: 0X00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIVDEFENA
r 		HFNMIENA
r 		ENABLE
r
Toggle Fields.

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

MPU_RNR

MPU region number register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGION
rw
Toggle Fields.

REGION

Bits 0-7: MPU region.

MPU_RBAR

MPU region base address register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw 		VALID
rw 		REGION
rw
Toggle Fields.

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

MPU_RASR

MPU region attribute and size register

Offset: 0x10, reset: 0X00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XN
rw 		AP
rw 		TEX
rw 		S
rw 		C
rw 		B
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD
rw 		SIZE
rw 		ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

2/82 fields covered. Toggle Registers.

ISER0

Interrupt Set-Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xE000EF00: Nested vectored interrupt controller

0/1 fields covered. Toggle Registers.

STIR

Software trigger interrupt register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
rw
Toggle Fields.

INTID

Bits 0-8: Software generated interrupt ID.

PKA

0x58002000: Public key accelerator

4/13 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRIE
rw 		RAMERRIE
rw 		PROCENDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE
rw 		START
rw 		EN
rw
Toggle Fields.

EN

Bit 0: PKA enable..

START

Bit 1: start the operation.

MODE

Bits 8-13: PKA operation code.

PROCENDIE

Bit 17: PROCENDIE.

RAMERRIE

Bit 19: RAM error interrupt enable.

ADDRERRIE

Bit 20: Address error interrupt enable.

SR

status register

Offset: 0x4, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRF
r 		RAMERRF
r 		PROCENDF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

BUSY

Bit 16: PKA operation is in progressThis bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started..

PROCENDF

Bit 17: PKA End of Operation flag.

RAMERRF

Bit 19: PKA RAM error flag.

ADDRERRF

Bit 20: Address error flag.

CLRFR

clear flag register

Offset: 0x8, reset: 0x00000000, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRFC
w 		RAMERRFC
w 		PROCENDFC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PROCENDFC

Bit 17: Clear PKA End of Operation flag.

RAMERRFC

Bit 19: Clear PKA RAM error flag.

ADDRERRFC

Bit 20: Clear Address error flag.

PWR

0x58000400: Power control

28/166 fields covered. Toggle Registers.

CR1

Power control register 1

Offset: 0x0, reset: 0x00000200, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR
rw 		VOS
rw 		DBP
rw 		FPDS
rw 		FPDR
rw 		SUBGHZSPINSSSEL
rw 		LPMS
rw
Toggle Fields.

LPMS

Bits 0-2: Low-power mode selection for CPU1.

SUBGHZSPINSSSEL

Bit 3: sub-GHz SPI NSS source select.

FPDR

Bit 4: Flash memory power down mode during LPRun for CPU1.

FPDS

Bit 5: Flash memory power down mode during LPSleep for CPU1.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVME3
rw 		PLS
rw 		PVDE
rw
Toggle Fields.

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection..

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

CR3

Power control register 3

Offset: 0x8, reset: 0x00008000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIWUL
rw 		EC2H
rw 		EWRFIRQ
rw 		EWRFBUSY
rw 		APC
rw 		RRS
rw 		EWPVD
rw 		EULPEN
rw 		EWUP3
rw 		EWUP2
rw 		EWUP1
rw
Toggle Fields.

EWUP1

Bit 0: Enable Wakeup pin WKUP1 for CPU1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2 for CPU1.

EWUP3

Bit 2: Enable Wakeup pin WKUP3 for CPU1.

EULPEN

Bit 7: Ultra-low-power enable.

EWPVD

Bit 8: Enable wakeup PVD for CPU1.

RRS

Bit 9: SRAM2 retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration from CPU1.

EWRFBUSY

Bit 11: Enable Radio BUSY Wakeup from Standby for CPU1.

EWRFIRQ

Bit 13: akeup for CPU1.

EC2H

Bit 14: nable CPU2 Hold interrupt for CPU1.

EIWUL

Bit 15: Enable internal wakeup line for CPU1.

CR4

Power control register 4

Offset: 0xC, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2BOOT
rw 		WRFBUSYP
rw 		VBRS
rw 		VBE
rw 		WP3
rw 		WP2
rw 		WP1
rw
Toggle Fields.

WP1

Bit 0: Wakeup pin WKUP1 polarity.

WP2

Bit 1: Wakeup pin WKUP2 polarity.

WP3

Bit 2: Wakeup pin WKUP3 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

WRFBUSYP

Bit 11: Wakeup Radio BUSY polarity.

C2BOOT

Bit 15: oot CPU2 after reset or wakeup from Stop or Standby modes..

SR1

Power status register 1

Offset: 0x10, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUFI
r 		C2HF
r 		WRFBUSYF
r 		WPVDF
r 		WUF3
r 		WUF2
r 		WUF1
r
Toggle Fields.

WUF1

Bit 0: Wakeup flag 1.

WUF2

Bit 1: Wakeup flag 2.

WUF3

Bit 2: Wakeup flag 3.

WPVDF

Bit 8: Wakeup PVD flag.

WRFBUSYF

Bit 11: Radio BUSY wakeup flag.

C2HF

Bit 14: PU2 Hold interrupt flag.

WUFI

Bit 15: Internal wakeup interrupt flag.

SR2

Power status register 2

Offset: 0x14, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO3
r 		PVDO
r 		VOSF
r 		REGLPF
r 		REGLPS
r 		FLASHRDY
r 		REGMRS
r 		RFEOLF
r 		LDORDY
r 		SMPSRDY
r 		RFBUSYMS
r 		RFBUSYS
r 		C2BOOTS
r
Toggle Fields.

C2BOOTS

Bit 0: PU2 boot/wakeup request source information.

RFBUSYS

Bit 1: Radio BUSY signal status.

RFBUSYMS

Bit 2: Radio BUSY masked signal status.

SMPSRDY

Bit 3: SMPS ready flag.

LDORDY

Bit 4: LDO ready flag.

RFEOLF

Bit 5: Radio end of life flag.

REGMRS

Bit 6: regulator2 low power flag.

FLASHRDY

Bit 7: Flash ready.

REGLPS

Bit 8: regulator1 started.

REGLPF

Bit 9: regulator1 low power flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

SCR

Power status clear register

Offset: 0x18, reset: 0x00000000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2HF
w 		CWRFBUSYF
w 		CWPVDF
w 		CWUF3
w 		CWUF2
w 		CWUF1
w
Toggle Fields.

CWUF1

Bit 0: Clear wakeup flag 1.

CWUF2

Bit 1: Clear wakeup flag 2.

CWUF3

Bit 2: Clear wakeup flag 3.

CWPVDF

Bit 8: Clear wakeup PVD interrupt flag.

CWRFBUSYF

Bit 11: Clear wakeup Radio BUSY flag.

CC2HF

Bit 14: lear CPU2 Hold interrupt flag.

CR5

Power control register 5

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSEN
rw 		RFEOLEN
rw
Toggle Fields.

RFEOLEN

Bit 14: Enable Radio End Of Life detector enabled.

SMPSEN

Bit 15: Enable SMPS Step Down converter SMPS mode enabled..

PUCRA

Power Port A pull-up control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle Fields.

PU0

Bit 0: PU0.

PU1

Bit 1: PU1.

PU2

Bit 2: PU2.

PU3

Bit 3: PU3.

PU4

Bit 4: PU4.

PU5

Bit 5: PU5.

PU6

Bit 6: PU6.

PU7

Bit 7: PU7.

PU8

Bit 8: PU8.

PU9

Bit 9: PU9.

PU10

Bit 10: PU10.

PU11

Bit 11: PU11.

PU12

Bit 12: PU12.

PU13

Bit 13: Port PA[y] pull-up bit y (y=0 to 13).

PU14

Bit 14: PU14.

PU15

Bit 15: Port PA15 pull-up.

PDCRA

Power Port A pull-down control register

Offset: 0x24, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle Fields.

PD0

Bit 0: PD0.

PD1

Bit 1: PD1.

PD2

Bit 2: PD2.

PD3

Bit 3: PD3.

PD4

Bit 4: PD4.

PD5

Bit 5: PD5.

PD6

Bit 6: PD6.

PD7

Bit 7: PD7.

PD8

Bit 8: PD8.

PD9

Bit 9: PD9.

PD10

Bit 10: PD10.

PD11

Bit 11: PD11.

PD12

Bit 12: Port PA[y] pull-down (y=0 to 12).

PD13

Bit 13: PD13.

PD14

Bit 14: ull-down.

PD15

Bit 15: PD15.

PUCRB

Power Port B pull-up control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle Fields.

PU0

Bit 0: PU0.

PU1

Bit 1: PU1.

PU2

Bit 2: PU2.

PU3

Bit 3: PU3.

PU4

Bit 4: PU4.

PU5

Bit 5: PU5.

PU6

Bit 6: PU6.

PU7

Bit 7: PU7.

PU8

Bit 8: PU8.

PU9

Bit 9: PU9.

PU10

Bit 10: PU10.

PU11

Bit 11: PU11.

PU12

Bit 12: PU12.

PU13

Bit 13: PU13.

PU14

Bit 14: PU14.

PU15

Bit 15: Port PB[y] pull-up (y=0 to 15).

PDCRB

Power Port B pull-down control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle Fields.

PD0

Bit 0: PD0.

PD1

Bit 1: PD1.

PD2

Bit 2: PD2.

PD3

Bit 3: Port PB[y] pull-down (y=0 to 3).

PD4

Bit 4: PD4.

PD5

Bit 5: PD5.

PD6

Bit 6: PD6.

PD7

Bit 7: PD7.

PD8

Bit 8: PD8.

PD9

Bit 9: PD9.

PD10

Bit 10: PD10.

PD11

Bit 11: PD11.

PD12

Bit 12: PD12.

PD13

Bit 13: PD13.

PD14

Bit 14: PD14.

PD15

Bit 15: Port PB[y] pull-down (y=5 to 15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle Fields.

PU0

Bit 0: PU0.

PU1

Bit 1: PU1.

PU2

Bit 2: PU2.

PU3

Bit 3: PU3.

PU4

Bit 4: PU4.

PU5

Bit 5: PU5.

PU6

Bit 6: PU6.

PU13

Bit 13: PU13.

PU14

Bit 14: PU14.

PU15

Bit 15: Port PC[y] pull-up (y=13 to 15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle Fields.

PD0

Bit 0: PD0.

PD1

Bit 1: PD1.

PD2

Bit 2: PD2.

PD3

Bit 3: PD3.

PD4

Bit 4: PD4.

PD5

Bit 5: PD5.

PD6

Bit 6: PD6.

PD13

Bit 13: PD13.

PD14

Bit 14: PD14.

PD15

Bit 15: Port PC[y] pull-down (y=13 to 15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU3
rw
Toggle Fields.

PU3

Bit 3: pull-up.

PDCRH

Power Port H pull-down control register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD3
rw
Toggle Fields.

PD3

Bit 3: pull-down.

C2CR1

Power CPU2 control register 1 [dual core device only]

Offset: 0x80, reset: 0x00000007, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPDS
rw 		FPDR
rw 		LPMS
rw
Toggle Fields.

LPMS

Bits 0-2: Low-power mode selection for CPU2.

FPDR

Bit 4: Flash memory power down mode during LPRun for CPU2.

FPDS

Bit 5: Flash memory power down mode during LPSleep for CPU2.

C2CR3

Power CPU2 control register 3 [dual core device only]

Offset: 0x84, reset: 0x00008000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIWUL
rw 		EWRFIRQ
rw 		EWRFBUSY
rw 		APC
rw 		EWPVD
rw 		EWUP3
rw 		EWUP2
rw 		EWUP1
rw
Toggle Fields.

EWUP1

Bit 0: Enable Wakeup pin WKUP1 for CPU2.

EWUP2

Bit 1: Enable Wakeup pin WKUP2 for CPU2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3 for CPU2.

EWPVD

Bit 8: Enable wakeup PVD for CPU2.

APC

Bit 10: Apply pull-up and pull-down configuration for CPU2.

EWRFBUSY

Bit 11: EWRFBUSY.

EWRFIRQ

Bit 13: akeup for CPU2.

EIWUL

Bit 15: Enable internal wakeup line for CPU2.

EXTSCR

Power extended status and status clear register

Offset: 0x88, reset: 0x00000000, access: Unspecified

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2DS
r 		C1DS
r 		C2STOPF
r 		C2STOP2F
r 		C2SBF
r 		C1STOPF
r 		C1STOP2F
r 		C1SBF
r 		C2CSSF
w 		C1CSSF
w
Toggle Fields.

C1CSSF

Bit 0: Clear CPU1 Stop Standby flags.

C2CSSF

Bit 1: lear CPU2 Stop Standby flags.

C1SBF

Bit 8: System Standby flag for CPU1. (no core states retained).

C1STOP2F

Bit 9: System Stop2 flag for CPU1. (partial core states retained).

C1STOPF

Bit 10: System Stop0, 1 flag for CPU1. (All core states retained).

C2SBF

Bit 11: ystem Standby flag for CPU2. (no core states retained).

C2STOP2F

Bit 12: ystem Stop2 flag for CPU2. (partial core states retained).

C2STOPF

Bit 13: ystem Stop0, 1 flag for CPU2. (All core states retained).

C1DS

Bit 14: CPU1 deepsleep mode.

C2DS

Bit 15: PU2 deepsleep mode.

SECCFGR

Power security configuration register [dual core device only]

Offset: 0x8C, reset: 0x00008000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2EWILA
rw
Toggle Fields.

C2EWILA

Bit 15: wakeup on CPU2 illegal access interrupt enable.

SUBGHZSPICR

Power SPI3 control register

Offset: 0x90, reset: 0x00008000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSS
rw
Toggle Fields.

NSS

Bit 15: sub-GHz SPI NSS control.

RSSCMDR

RSS Command register [dual core device only]

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSSCMD
rw
Toggle Fields.

RSSCMD

Bits 0-7: RSS command.

RCC

0x58000000: Reset and clock control

34/274 fields covered. Toggle Registers.

CR

Clock control register

Offset: 0x0, reset: 0x00000061, access: Unspecified

5/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLRDY
r 		PLLON
rw 		HSEBYPPWR
rw 		HSEPRE
rw 		CSSON
rw 		HSERDY
r 		HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIKERDY
r 		HSIASFS
rw 		HSIRDY
r 		HSIKERON
rw 		HSION
rw 		MSIRANGE
rw 		MSIRGSEL
rw 		MSIPLLEN
rw 		MSIRDY
r 		MSION
rw
Toggle Fields.

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready).

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRGSEL

Bit 3: MSI range control selection.

MSIRANGE

Bits 4-7: MSI clock ranges.

HSION

Bit 8: HSI16 clock enable.

HSIKERON

Bit 9: HSI16 always enable for peripheral kernel clocks..

HSIRDY

Bit 10: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready).

HSIASFS

Bit 11: HSI16 automatic start from Stop.

HSIKERDY

Bit 12: HSI16 kernel clock ready flag for peripherals requests..

HSEON

Bit 16: HSE32 clock enable.

HSERDY

Bit 17: HSE32 clock ready flag.

CSSON

Bit 19: HSE32 Clock security system enable.

HSEPRE

Bit 20: HSE32 sysclk prescaler.

HSEBYPPWR

Bit 21: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO..

PLLON

Bit 24: Main PLL enable.

PLLRDY

Bit 25: Main PLL clock ready flag.

ICSCR

Internal clock sources calibration register

Offset: 0x4, reset: 0x40000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw 		HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM
rw 		MSICAL
r
Toggle Fields.

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI16 clock calibration.

HSITRIM

Bits 24-30: HSI16 clock trimming.

CFGR

Clock configuration register

Offset: 0x8, reset: 0x00070000, access: Unspecified

4/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
rw 		MCOSEL
rw 		PPRE2F
r 		PPRE1F
r 		HPREF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK
rw 		PPRE2
rw 		PPRE1
rw 		HPRE
rw 		SWS
r 		SW
rw
Toggle Fields.

SW

Bits 0-1: System clock switch.

SWS

Bits 2-3: System clock switch status.

HPRE

Bits 4-7: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.).

PPRE1

Bits 8-10: PCLK1 low-speed prescaler (APB1).

PPRE2

Bits 11-13: PCLK2 high-speed prescaler (APB2).

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

HPREF

Bit 16: HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1).

PPRE1F

Bit 17: PCLK1 prescaler flag (APB1).

PPRE2F

Bit 18: PCLK2 prescaler flag (APB2).

MCOSEL

Bits 24-27: Microcontroller clock output.

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

PLLCFGR

PLL configuration register

Offset: 0xC, reset: 0x22040100, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLR
rw 		PLLREN
rw 		PLLQ
rw 		PLLQEN
rw 		PLLP
rw 		PLLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw 		PLLM
rw 		PLLSRC
rw
Toggle Fields.

PLLSRC

Bits 0-1: Main PLL entry clock source.

PLLM

Bits 4-6: Division factor for the main PLL input clock.

PLLN

Bits 8-14: Main PLL multiplication factor for VCO.

PLLPEN

Bit 16: Main PLL PLLPCLK output enable.

PLLP

Bits 17-21: Main PLL division factor for PLLPCLK..

PLLQEN

Bit 24: Main PLL PLLQCLK output enable.

PLLQ

Bits 25-27: Main PLL division factor for PLLQCLK.

PLLREN

Bit 28: Main PLL PLLRCLK output enable.

PLLR

Bits 29-31: Main PLL division factor for PLLRCLK.

CIER

Clock interrupt enable register

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSIE
rw 		PLLRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		MSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw
Toggle Fields.

LSIRDYIE

Bit 0: LSI ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI16 ready interrupt enable.

HSERDYIE

Bit 4: HSE32 ready interrupt enable.

PLLRDYIE

Bit 5: PLL ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1C, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSF
r 		CSSF
r 		PLLRDYF
r 		HSERDYF
r 		HSIRDYF
r 		MSIRDYF
r 		LSERDYF
r 		LSIRDYF
r
Toggle Fields.

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI16 ready interrupt flag.

HSERDYF

Bit 4: HSE32 ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

CSSF

Bit 8: HSE32 Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, reset: 0x00000000, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSC
w 		CSSC
w 		PLLRDYC
w 		HSERDYC
w 		HSIRDYC
w 		MSIRDYC
w 		LSERDYC
w 		LSIRDYC
w
Toggle Fields.

LSIRDYC

Bit 0: LSI ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI16 ready interrupt clear.

HSERDYC

Bit 4: HSE32 ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

CSSC

Bit 8: HSE32 Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, reset: 0x000000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw 		DMAMUX1RST
rw 		DMA2RST
rw 		DMA1RST
rw
Toggle Fields.

DMA1RST

Bit 0: DMA1 reset.

DMA2RST

Bit 1: DMA2 reset.

DMAMUX1RST

Bit 2: DMAMUX1 reset.

CRCRST

Bit 12: CRC reset.

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2C, reset: 0x000000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOHRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle Fields.

GPIOARST

Bit 0: IO port A reset.

GPIOBRST

Bit 1: IO port B reset.

GPIOCRST

Bit 2: IO port C reset.

GPIOHRST

Bit 7: IO port H reset.

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, reset: 0x000000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASHRST
rw 		IPCCRST
rw 		HSEMRST
rw 		RNGRST
rw 		AESRST
rw 		PKARST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PKARST

Bit 16: PKARST.

AESRST

Bit 17: AESRST.

RNGRST

Bit 18: RNGRST.

HSEMRST

Bit 19: HSEMRST.

IPCCRST

Bit 20: IPCCRST.

FLASHRST

Bit 25: Flash interface reset.

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1RST
rw 		DACRST
rw 		I2C3RST
rw 		I2C2RST
rw 		I2C1RST
rw 		USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S2RST
rw 		TIM2RST
rw
Toggle Fields.

TIM2RST

Bit 0: TIM2 timer reset.

SPI2S2RST

Bit 14: SPI2S2 reset.

USART2RST

Bit 17: USART2 reset.

I2C1RST

Bit 21: I2C1 reset.

I2C2RST

Bit 22: I2C2 reset.

I2C3RST

Bit 23: I2C3 reset.

DACRST

Bit 29: DAC1 reset.

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3C, reset: 0x000000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3RST
rw 		LPTIM2RST
rw 		LPUART1RST
rw
Toggle Fields.

LPUART1RST

Bit 0: Low-power UART 1 reset.

LPTIM2RST

Bit 5: Low-power timer 2 reset.

LPTIM3RST

Bit 6: Low-power timer 3 reset.

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, reset: 0x000000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17RST
rw 		TIM16RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		SPI1RST
rw 		TIM1RST
rw 		ADCRST
rw
Toggle Fields.

ADCRST

Bit 9: ADC reset.

TIM1RST

Bit 11: TIM1 timer reset.

SPI1RST

Bit 12: SPI1 reset.

USART1RST

Bit 14: USART1 reset.

TIM16RST

Bit 17: TIM16 timer reset.

TIM17RST

Bit 18: TIM17 timer reset.

APB3RSTR

APB3 peripheral reset register

Offset: 0x44, reset: 0x000000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBGHZSPIRST
rw
Toggle Fields.

SUBGHZSPIRST

Bit 0: Sub-GHz radio SPI reset.

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		DMAMUX1EN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle Fields.

DMA1EN

Bit 0: CPU1 DMA1 clock enable.

DMA2EN

Bit 1: CPU1 DMA2 clock enable.

DMAMUX1EN

Bit 2: CPU1 DMAMUX1 clock enable.

CRCEN

Bit 12: CPU1 CRC clock enable.

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOHEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle Fields.

GPIOAEN

Bit 0: CPU1 IO port A clock enable.

GPIOBEN

Bit 1: CPU1 IO port B clock enable.

GPIOCEN

Bit 2: CPU1 IO port C clock enable.

GPIOHEN

Bit 7: CPU1 IO port H clock enable.

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, reset: 0x02080000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASHEN
rw 		IPCCEN
rw 		HSEMEN
rw 		RNGEN
rw 		AESEN
rw 		PKAEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PKAEN

Bit 16: PKAEN.

AESEN

Bit 17: AESEN.

RNGEN

Bit 18: RNGEN.

HSEMEN

Bit 19: HSEMEN.

IPCCEN

Bit 20: IPCCEN.

FLASHEN

Bit 25: CPU1 Flash interface clock enable.

APB1ENR1

APB1 peripheral clock enable register 1

Offset: 0x58, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw 		DAC1EN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S2EN
rw 		WWDGEN
rw 		RTCAPBEN
rw 		TIM2EN
rw
Toggle Fields.

TIM2EN

Bit 0: CPU1 TIM2 timer clock enable.

RTCAPBEN

Bit 10: CPU1 RTC APB clock enable.

WWDGEN

Bit 11: CPU1 Window watchdog clock enable.

SPI2S2EN

Bit 14: CPU1 SPI2S2 clock enable.

USART2EN

Bit 17: CPU1 USART2 clock enable.

I2C1EN

Bit 21: CPU1 I2C1 clocks enable.

I2C2EN

Bit 22: CPU1 I2C2 clocks enable.

I2C3EN

Bit 23: CPU1 I2C3 clocks enable.

DAC1EN

Bit 29: CPU1 DAC1 clock enable.

LPTIM1EN

Bit 31: CPU1 Low power timer 1 clocks enable.

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5C, reset: 0x000000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3EN
rw 		LPTIM2EN
rw 		LPUART1EN
rw
Toggle Fields.

LPUART1EN

Bit 0: CPU1 Low power UART 1 clocks enable.

LPTIM2EN

Bit 5: CPU1 Low power timer 2 clocks enable.

LPTIM3EN

Bit 6: CPU1 Low power timer 3 clocks enable.

APB2ENR

APB2 peripheral clock enable register

Offset: 0x60, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17EN
rw 		TIM16EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw 		SPI1EN
rw 		TIM1EN
rw 		ADCEN
rw
Toggle Fields.

ADCEN

Bit 9: CPU1 ADC clocks enable.

TIM1EN

Bit 11: CPU1 TIM1 timer clock enable.

SPI1EN

Bit 12: CPU1 SPI1 clock enable.

USART1EN

Bit 14: CPU1 USART1clocks enable.

TIM16EN

Bit 17: CPU1 TIM16 timer clock enable.

TIM17EN

Bit 18: CPU1 TIM17 timer clock enable.

APB3ENR

APB3 peripheral clock enable register

Offset: 0x64, reset: 0x000000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBGHZSPIEN
rw
Toggle Fields.

SUBGHZSPIEN

Bit 0: sub-GHz radio SPI clock enable.

AHB1SMENR

AHB1 peripheral clocks enable in Sleep modes register

Offset: 0x68, reset: 0x00001007, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw 		DMAMUX1SMEN
rw 		DMA2SMEN
rw 		DMA1SMEN
rw
Toggle Fields.

DMA1SMEN

Bit 0: DMA1 clock enable during CPU1 CSleep mode..

DMA2SMEN

Bit 1: DMA2 clock enable during CPU1 CSleep mode.

DMAMUX1SMEN

Bit 2: DMAMUX1 clock enable during CPU1 CSleep mode..

CRCSMEN

Bit 12: CRC clock enable during CPU1 CSleep mode..

AHB2SMENR

AHB2 peripheral clocks enable in Sleep modes register

Offset: 0x6C, reset: 0x00000087, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOHSMEN
rw 		GPIOCSMEN
rw 		GPIOBSMEN
rw 		GPIOASMEN
rw
Toggle Fields.

GPIOASMEN

Bit 0: IO port A clock enable during CPU1 CSleep mode..

GPIOBSMEN

Bit 1: IO port B clock enable during CPU1 CSleep mode..

GPIOCSMEN

Bit 2: IO port C clock enable during CPU1 CSleep mode..

GPIOHSMEN

Bit 7: IO port H clock enable during CPU1 CSleep mode..

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, reset: 0x03870000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASHSMEN
rw 		SRAM2SMEN
rw 		SRAM1SMEN
rw 		RNGSMEN
rw 		AESSMEN
rw 		PKASMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PKASMEN

Bit 16: PKA accelerator clock enable during CPU1 CSleep mode..

AESSMEN

Bit 17: AES accelerator clock enable during CPU1 CSleep mode..

RNGSMEN

Bit 18: True RNG clocks enable during CPU1 Csleep and CStop modes.

SRAM1SMEN

Bit 23: SRAM1 interface clock enable during CPU1 CSleep mode..

SRAM2SMEN

Bit 24: SRAM2 memory interface clock enable during CPU1 CSleep mode.

FLASHSMEN

Bit 25: Flash interface clock enable during CPU1 CSleep mode..

APB1SMENR1

APB1 peripheral clocks enable in Sleep mode register 1

Offset: 0x78, reset: 0xA0E24C01, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SMEN
rw 		DACSMEN
rw 		I2C3SMEN
rw 		I2C2SMEN
rw 		I2C1SMEN
rw 		USART2SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S2SMEN
rw 		WWDGSMEN
rw 		RTCAPBSMEN
rw 		TIM2SMEN
rw
Toggle Fields.

TIM2SMEN

Bit 0: TIM2 timer clock enable during CPU1 CSleep mode..

RTCAPBSMEN

Bit 10: RTC bus clock enable during CPU1 CSleep mode..

WWDGSMEN

Bit 11: Window watchdog clocks enable during CPU1 CSleep mode..

SPI2S2SMEN

Bit 14: SPI2S2 clock enable during CPU1 CSleep mode..

USART2SMEN

Bit 17: USART2 clock enable during CPU1 CSleep mode..

I2C1SMEN

Bit 21: I2C1 clock enable during CPU1 Csleep and CStop modes.

I2C2SMEN

Bit 22: I2C2 clock enable during CPU1 Csleep and CStop modes.

I2C3SMEN

Bit 23: I2C3 clock enable during CPU1 Csleep and CStop modes.

DACSMEN

Bit 29: DAC1 clock enable during CPU1 CSleep mode..

LPTIM1SMEN

Bit 31: Low power timer 1 clock enable during CPU1 Csleep and CStop mode.

APB1SMENR2

APB1 peripheral clocks enable in Sleep mode register 2

Offset: 0x7C, reset: 0x00000061, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3SMEN
rw 		LPTIM2SMEN
rw 		LPUART1SMEN
rw
Toggle Fields.

LPUART1SMEN

Bit 0: Low power UART 1 clock enable during CPU1 Csleep and CStop modes..

LPTIM2SMEN

Bit 5: Low power timer 2 clock enable during CPU1 Csleep and CStop modes.

LPTIM3SMEN

Bit 6: Low power timer 3 clock enable during CPU1 Csleep and CStop modes.

APB2SMENR

APB2 peripheral clocks enable in Sleep mode register

Offset: 0x80, reset: 0x00065A00, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17SMEN
rw 		TIM16SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw 		SPI1SMEN
rw 		TIM1SMEN
rw 		ADCSMEN
rw
Toggle Fields.

ADCSMEN

Bit 9: ADC clocks enable during CPU1 Csleep and CStop modes.

TIM1SMEN

Bit 11: TIM1 timer clock enable during CPU1 CSleep mode..

SPI1SMEN

Bit 12: SPI1 clock enable during CPU1 CSleep mode..

USART1SMEN

Bit 14: USART1 clock enable during CPU1 Csleep and CStop modes..

TIM16SMEN

Bit 17: TIM16 timer clock enable during CPU1 CSleep mode..

TIM17SMEN

Bit 18: TIM17 timer clock enable during CPU1 CSleep mode..

APB3SMENR

APB3 peripheral clock enable in Sleep mode register

Offset: 0x84, reset: 0x000000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBGHZSPISMEN
rw
Toggle Fields.

SUBGHZSPISMEN

Bit 0: Sub-GHz radio SPI clock enable during Sleep and Stop modes.

CCIPR

Peripherals independent clock configuration register

Offset: 0x88, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNGSEL
rw 		ADCSEL
rw 		LPTIM3SEL
rw 		LPTIM2SEL
rw 		LPTIM1SEL
rw 		I2C3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw 		I2C1SEL
rw 		LPUART1SEL
rw 		SPI2S2SEL
rw 		USART2SEL
rw 		USART1SEL
rw
Toggle Fields.

USART1SEL

Bits 0-1: USART1 clock source selection.

USART2SEL

Bits 2-3: USART2 clock source selection.

SPI2S2SEL

Bits 8-9: SPI2S2 I2S clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2C2SEL

Bits 14-15: I2C2 clock source selection.

I2C3SEL

Bits 16-17: I2C3 clock source selection.

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

LPTIM3SEL

Bits 22-23: Low power timer 3 clock source selection.

ADCSEL

Bits 28-29: ADC clock source selection.

RNGSEL

Bits 30-31: RNG clock source selection.

BDCR

Backup domain control register

Offset: 0x90, reset: 0x00000000, access: Unspecified

3/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOSEL
rw 		LSCOEN
rw 		BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		LSESYSRDY
r 		RTCSEL
rw 		LSESYSEN
rw 		LSECSSD
r 		LSECSSON
rw 		LSEDRV
rw 		LSEBYP
rw 		LSERDY
r 		LSEON
rw
Toggle Fields.

LSEON

Bit 0: LSE oscillator enable.

LSERDY

Bit 1: LSE oscillator ready.

LSEBYP

Bit 2: LSE oscillator bypass.

LSEDRV

Bits 3-4: LSE oscillator drive capability.

LSECSSON

Bit 5: CSS on LSE enable.

LSECSSD

Bit 6: CSS on LSE failure Detection.

LSESYSEN

Bit 7: LSE system clock enable.

RTCSEL

Bits 8-9: RTC clock source selection.

LSESYSRDY

Bit 11: LSE system clock ready.

RTCEN

Bit 15: RTC clock enable.

BDRST

Bit 16: Backup domain software reset.

LSCOEN

Bit 24: Low speed clock output enable.

LSCOSEL

Bit 25: Low speed clock output selection.

CSR

Control/status register

Offset: 0x94, reset: 0x0C01C600, access: Unspecified

10/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRRSTF
r 		WWDGRSTF
r 		IWDGRSTF
r 		SFTRSTF
r 		BORRSTF
r 		PINRSTF
r 		OBLRSTF
r 		RFILARSTF
r 		RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFRST
rw 		RFRSTF
r 		MSISRANGE
rw 		LSIPRE
rw 		LSIRDY
r 		LSION
rw
Toggle Fields.

LSION

Bit 0: LSI oscillator enable.

LSIRDY

Bit 1: LSI oscillator ready.

LSIPRE

Bit 4: LSI frequency prescaler.

MSISRANGE

Bits 8-11: MSI clock ranges.

RFRSTF

Bit 14: Radio in reset status flag.

RFRST

Bit 15: Radio reset.

RMVF

Bit 23: Remove reset flag.

RFILARSTF

Bit 24: Radio illegal access flag.

OBLRSTF

Bit 25: Option byte loader reset flag.

PINRSTF

Bit 26: Pin reset flag.

BORRSTF

Bit 27: BOR flag.

SFTRSTF

Bit 28: Software reset flag.

IWDGRSTF

Bit 29: Independent window watchdog reset flag.

WWDGRSTF

Bit 30: Window watchdog reset flag.

LPWRRSTF

Bit 31: Low-power reset flag.

EXTCFGR

Extended clock recovery register

Offset: 0x108, reset: 0x00030000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C2HPREF
r 		SHDHPREF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2HPRE
rw 		SHDHPRE
rw
Toggle Fields.

SHDHPRE

Bits 0-3: HCLK3 shared prescaler (AHB3, Flash, and SRAM2).

C2HPRE

Bits 4-7: [dual core device only] HCLK2 prescaler (CPU2).

SHDHPREF

Bit 16: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2).

C2HPREF

Bit 17: CLK2 prescaler flag (CPU2).

C2AHB1ENR

CPU2 AHB1 peripheral clock enable register

Offset: 0x148, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		DMAMUX1EN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle Fields.

DMA1EN

Bit 0: CPU2 DMA1 clock enable.

DMA2EN

Bit 1: CPU2 DMA2 clock enable.

DMAMUX1EN

Bit 2: CPU2 DMAMUX1 clock enable.

CRCEN

Bit 12: CPU2 CRC clock enable.

C2AHB2ENR

CPU2 AHB2 peripheral clock enable register

Offset: 0x14C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOHEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle Fields.

GPIOAEN

Bit 0: CPU2 IO port A clock enable.

GPIOBEN

Bit 1: CPU2 IO port B clock enable.

GPIOCEN

Bit 2: CPU2 IO port C clock enable.

GPIOHEN

Bit 7: CPU2 IO port H clock enable.

C2AHB3ENR

CPU2 AHB3 peripheral clock enable register [dual core device only]

Offset: 0x150, reset: 0x02080000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASHEN
rw 		IPCCEN
rw 		HSEMEN
rw 		RNGEN
rw 		AESEN
rw 		PKAEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PKAEN

Bit 16: CPU2 PKA accelerator clock enable.

AESEN

Bit 17: CPU2 AES accelerator clock enable.

RNGEN

Bit 18: CPU2 True RNG clocks enable.

HSEMEN

Bit 19: CPU2 HSEM clock enable.

IPCCEN

Bit 20: CPU2 IPCC interface clock enable.

FLASHEN

Bit 25: CPU2 Flash interface clock enable.

C2APB1ENR1

CPU2 APB1 peripheral clock enable register 1 [dual core device only]

Offset: 0x158, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw 		DAC1EN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S2EN
rw 		RTCAPBEN
rw 		TIM2EN
rw
Toggle Fields.

TIM2EN

Bit 0: CPU2 TIM2 timer clock enable.

RTCAPBEN

Bit 10: CPU2 RTC APB clock enable.

SPI2S2EN

Bit 14: CPU2 SPI2S2 clock enable.

USART2EN

Bit 17: CPU2 USART2 clock enable.

I2C1EN

Bit 21: CPU2 I2C1 clocks enable.

I2C2EN

Bit 22: CPU2 I2C2 clocks enable.

I2C3EN

Bit 23: CPU2 I2C3 clocks enable.

DAC1EN

Bit 29: CPU2 DAC1 clock enable.

LPTIM1EN

Bit 31: CPU2 Low power timer 1 clocks enable.

C2APB1ENR2

CPU2 APB1 peripheral clock enable register 2 [dual core device only]

Offset: 0x15C, reset: 0x000000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3EN
rw 		LPTIM2EN
rw 		LPUART1EN
rw
Toggle Fields.

LPUART1EN

Bit 0: CPU2 Low power UART 1 clocks enable.

LPTIM2EN

Bit 5: CPU2 Low power timer 2 clocks enable.

LPTIM3EN

Bit 6: CPU2 Low power timer 3 clocks enable.

C2APB2ENR

CPU2 APB2 peripheral clock enable register [dual core device only]

Offset: 0x160, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17EN
rw 		TIM16EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw 		SPI1EN
rw 		TIM1EN
rw 		ADCEN
rw
Toggle Fields.

ADCEN

Bit 9: ADC clocks enable.

TIM1EN

Bit 11: CPU2 TIM1 timer clock enable.

SPI1EN

Bit 12: CPU2 SPI1 clock enable.

USART1EN

Bit 14: CPU2 USART1clocks enable.

TIM16EN

Bit 17: CPU2 TIM16 timer clock enable.

TIM17EN

Bit 18: CPU2 TIM17 timer clock enable.

C2APB3ENR

CPU2 APB3 peripheral clock enable register [dual core device only]

Offset: 0x164, reset: 0x000000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBGHZSPIEN
rw
Toggle Fields.

SUBGHZSPIEN

Bit 0: CPU2 sub-GHz radio SPI clock enable.

C2AHB1SMENR

CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]

Offset: 0x168, reset: 0x00001007, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw 		DMAMUX1SMEN
rw 		DMA2SMEN
rw 		DMA1SMEN
rw
Toggle Fields.

DMA1SMEN

Bit 0: DMA1 clock enable during CPU2 CSleep mode..

DMA2SMEN

Bit 1: DMA2 clock enable during CPU2 CSleep mode..

DMAMUX1SMEN

Bit 2: DMAMUX1 clock enable during CPU2 CSleep mode..

CRCSMEN

Bit 12: CRC clock enable during CPU2 CSleep mode..

C2AHB2SMENR

CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]

Offset: 0x16C, reset: 0x00000087, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOHSMEN
rw 		GPIOCSMEN
rw 		GPIOBSMEN
rw 		GPIOASMEN
rw
Toggle Fields.

GPIOASMEN

Bit 0: IO port A clock enable during CPU2 CSleep mode..

GPIOBSMEN

Bit 1: IO port B clock enable during CPU2 CSleep mode..

GPIOCSMEN

Bit 2: IO port C clock enable during CPU2 CSleep mode..

GPIOHSMEN

Bit 7: IO port H clock enable during CPU2 CSleep mode..

C2AHB3SMENR

CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]

Offset: 0x170, reset: 0x03870000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASHSMEN
rw 		SRAM2SMEN
rw 		SRAM1SMEN
rw 		RNGSMEN
rw 		AESSMEN
rw 		PKASMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PKASMEN

Bit 16: PKA accelerator clock enable during CPU2 CSleep mode..

AESSMEN

Bit 17: AES accelerator clock enable during CPU2 CSleep mode..

RNGSMEN

Bit 18: True RNG clock enable during CPU2 CSleep and CStop mode..

SRAM1SMEN

Bit 23: SRAM1 interface clock enable during CPU2 CSleep mode..

SRAM2SMEN

Bit 24: SRAM2 memory interface clock enable during CPU2 CSleep mode..

FLASHSMEN

Bit 25: Flash interface clock enable during CPU2 CSleep mode..

C2APB1SMENR1

CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]

Offset: 0x178, reset: 0xA0E24401, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SMEN
rw 		DAC1SMEN
rw 		I2C3SMEN
rw 		I2C2SMEN
rw 		I2C1SMEN
rw 		USART2SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S2SMEN
rw 		RTCAPBSMEN
rw 		TIM2SMEN
rw
Toggle Fields.

TIM2SMEN

Bit 0: TIM2 timer clock enable during CPU2 CSleep mode..

RTCAPBSMEN

Bit 10: RTC bus clock enable during CPU2 CSleep mode..

SPI2S2SMEN

Bit 14: SPI2S2 clock enable during CPU2 CSleep mode..

USART2SMEN

Bit 17: USART2 clock enable during CPU2 CSleep mode..

I2C1SMEN

Bit 21: I2C1 clock enable during CPU2 CSleep and CStop modes.

I2C2SMEN

Bit 22: I2C2 clock enable during CPU2 CSleep and CStop modes.

I2C3SMEN

Bit 23: I2C3 clock enable during CPU2 CSleep and CStop modes.

DAC1SMEN

Bit 29: DAC1 clock enable during CPU2 CSleep mode..

LPTIM1SMEN

Bit 31: Low power timer 1 clock enable during CPU2 CSleep and CStop mode.

C2APB1SMENR2

CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]

Offset: 0x17C, reset: 0x00000061, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3SMEN
rw 		LPTIM2SMEN
rw 		LPUART1SMEN
rw
Toggle Fields.

LPUART1SMEN

Bit 0: Low power UART 1 clock enable during CPU2 CSleep and CStop mode.

LPTIM2SMEN

Bit 5: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes..

LPTIM3SMEN

Bit 6: Low power timer 3 clocks enable during CPU2 CSleep and CStop modes..

C2APB2SMENR

CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]

Offset: 0x180, reset: 0x00065A00, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17SMEN
rw 		TIM16SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw 		SPI1SMEN
rw 		TIM1SMEN
rw 		ADCSMEN
rw
Toggle Fields.

ADCSMEN

Bit 9: ADC clocks enable during CPU2 Csleep and CStop modes.

TIM1SMEN

Bit 11: TIM1 timer clock enable during CPU2 CSleep mode.

SPI1SMEN

Bit 12: SPI1 clock enable during CPU2 CSleep mode.

USART1SMEN

Bit 14: USART1clock enable during CPU2 CSleep and CStop mode.

TIM16SMEN

Bit 17: TIM16 timer clock enable during CPU2 CSleep mode.

TIM17SMEN

Bit 18: TIM17 timer clock enable during CPU2 CSleep mode.

C2APB3SMENR

CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]

Offset: 0x184, reset: 0x000000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBGHZSPISMEN
rw
Toggle Fields.

SUBGHZSPISMEN

Bit 0: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes.

RNG

0x58001000: True random number generator

4/17 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00800000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONFIGLOCK
rw 		CONDRST
rw 		RNG_CONFIG1
rw 		CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG_CONFIG2
rw 		NISTC
rw 		RNG_CONFIG3
rw 		CED
rw 		IE
rw 		RNGEN
rw
Toggle Fields.

RNGEN

Bit 2: True random number generator enable.

IE

Bit 3: Interrupt Enable.

CED

Bit 5: Interrupt Enable.

RNG_CONFIG3

Bits 8-11: RNG_CONFIG3.

NISTC

Bit 12: NISTC.

RNG_CONFIG2

Bits 13-15: RNG_CONFIG2.

CLKDIV

Bits 16-19: CLKDIV.

RNG_CONFIG1

Bits 20-25: RNG_CONFIG1.

CONDRST

Bit 30: Conditioning soft reset.

CONFIGLOCK

Bit 31: CONFIGLOCK.

SR

status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw 		CEIS
rw 		SECS
r 		CECS
r 		DRDY
r
Toggle Fields.

DRDY

Bit 0: Data Ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle Fields.

RNDATA

Bits 0-31: Random data.

HTCR

health test control register

Offset: 0x10, reset: 0x00005A4E, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTCFG
rw
Toggle Fields.

HTCFG

Bits 0-31: health test configuration.

RTC

0x40002800: Real-time clock

33/133 fields covered. Toggle Registers.

TR

TR

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

DR

Offset: 0x4, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle Fields.

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

SSR

SSR

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle Fields.

SS

Bits 0-31: Synchronous binary counter.

ICSR

ICSR

Offset: 0xC, reset: 0x00000007, access: Unspecified

5/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCDU
rw 		BIN
rw 		INIT
rw 		INITF
r 		RSF
rw 		INITS
r 		SHPF
r 		WUTWF
r
Toggle Fields.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

BIN

Bits 8-9: Binary mode.

BCDU

Bits 10-12: BCD update.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

PRER

Offset: 0x10, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle Fields.

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

WUTR

Offset: 0x14, reset: 0x0000FFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUTOCLR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle Fields.

WUT

Bits 0-15: Wakeup auto-reload value bits.

WUTOCLR

Bits 16-31: Wakeup auto-reload output clear value.

CR

CR

Offset: 0x18, reset: 0x00000000, access: Unspecified

0/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2EN
rw 		TAMPALRM_TYPE
rw 		TAMPALRM_PU
rw 		TAMPOE
rw 		TAMPTS
rw 		ITSE
rw 		COE
rw 		OSEL
rw 		POL
rw 		COSEL
rw 		BKP
rw 		SUB1H
w 		ADD1H
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALRBIE
rw 		ALRAIE
rw 		TSE
rw 		WUTE
rw 		ALRBE
rw 		ALRAE
rw 		SSRUIE
rw 		FMT
rw 		BYPSHAD
rw 		REFCKON
rw 		TSEDGE
rw 		WUCKSEL
rw
Toggle Fields.

WUCKSEL

Bits 0-2: Wakeup clock selection.

TSEDGE

Bit 3: Timestamp event active edge.

REFCKON

Bit 4: RTC_REFIN reference clock detection enable (50 or 60 Hz).

BYPSHAD

Bit 5: Bypass the shadow registers.

FMT

Bit 6: Hour format.

SSRUIE

Bit 7: SSR underflow interrupt enable.

ALRAE

Bit 8: Alarm A enable.

ALRBE

Bit 9: Alarm B enable.

WUTE

Bit 10: Wakeup timer enable.

TSE

Bit 11: timestamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

ALRBIE

Bit 13: Alarm B interrupt enable.

WUTIE

Bit 14: Wakeup timer interrupt enable.

TSIE

Bit 15: Timestamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change).

SUB1H

Bit 17: Subtract 1 hour (winter time change).

BKP

Bit 18: Backup.

COSEL

Bit 19: Calibration output selection.

POL

Bit 20: Output polarity.

OSEL

Bits 21-22: Output selection.

COE

Bit 23: Calibration output enable.

ITSE

Bit 24: timestamp on internal event enable.

TAMPTS

Bit 25: Activate timestamp on tamper detection event.

TAMPOE

Bit 26: Tamper detection output enable on TAMPALRM.

TAMPALRM_PU

Bit 29: TAMPALRM pull-up enable.

TAMPALRM_TYPE

Bit 30: TAMPALRM output type.

OUT2EN

Bit 31: RTC_OUT2 output enable.

WPR

write protection register

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-7: Write protection key.

CALR

CALR

Offset: 0x28, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		LPCAL
rw 		CALM
rw
Toggle Fields.

CALM

Bits 0-8: Calibration minus.

LPCAL

Bit 12: Calibration low-power mode.

CALW16

Bit 13: CALW16.

CALW8

Bit 14: Use a 16-second calibration cycle period.

CALP

Bit 15: Use an 8-second calibration cycle period.

SHIFTR

SHIFTR

Offset: 0x2C, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle Fields.

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

TSTR

Offset: 0x30, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
r 		HT
r 		HU
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
r 		MNU
r 		ST
r 		SU
r
Toggle Fields.

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation.

TSDR

TSDR

Offset: 0x34, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
r 		MT
r 		MU
r 		DT
r 		DU
r
Toggle Fields.

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

TSSSR

Offset: 0x38, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle Fields.

SS

Bits 0-31: Sub second value.

ALRMAR

ALRMAR

Offset: 0x40, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMASSR

ALRMASSR

Offset: 0x44, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCLR
rw 		MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle Fields.

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-29: Mask the most-significant bits starting at this bit.

SSCLR

Bit 31: Clear synchronous counter on alarm (Binary mode only).

ALRMBR

ALRMBR

Offset: 0x48, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm B seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm B minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm B hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm B date mask.

ALRMBSSR

ALRMBSSR

Offset: 0x4C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCLR
rw 		MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle Fields.

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-29: Mask the most-significant bits starting at this bit.

SSCLR

Bit 31: Clear synchronous counter on alarm (Binary mode only).

SR

SR

Offset: 0x50, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRUF
r 		ITSF
r 		TSOVF
r 		TSF
r 		WUTF
r 		ALRBF
r 		ALRAF
r
Toggle Fields.

ALRAF

Bit 0: Alarm A flag.

ALRBF

Bit 1: Alarm B flag.

WUTF

Bit 2: Wakeup timer flag.

TSF

Bit 3: Timestamp flag.

TSOVF

Bit 4: Timestamp overflow flag.

ITSF

Bit 5: Internal timestamp flag.

SSRUF

Bit 6: SSR underflow flag.

MISR

MISR

Offset: 0x54, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRUMF
r 		ITSMF
r 		TSOVMF
r 		TSMF
r 		WUTMF
r 		ALRBMF
r 		ALRAMF
r
Toggle Fields.

ALRAMF

Bit 0: Alarm A masked flag.

ALRBMF

Bit 1: Alarm B masked flag.

WUTMF

Bit 2: Wakeup timer masked flag.

TSMF

Bit 3: Timestamp masked flag.

TSOVMF

Bit 4: Timestamp overflow masked flag.

ITSMF

Bit 5: Internal timestamp masked flag.

SSRUMF

Bit 6: SSR underflow masked flag.

SCR

SCR

Offset: 0x5C, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSSRUF
w 		CITSF
w 		CTSOVF
w 		CTSF
w 		CWUTF
w 		CALRBF
w 		CALRAF
w
Toggle Fields.

CALRAF

Bit 0: Clear alarm A flag.

CALRBF

Bit 1: Clear alarm B flag.

CWUTF

Bit 2: Clear wakeup timer flag.

CTSF

Bit 3: Clear timestamp flag.

CTSOVF

Bit 4: Clear timestamp overflow flag.

CITSF

Bit 5: Clear internal timestamp flag.

CSSRUF

Bit 6: Clear SSR underflow flag.

ALRABINR

RTC alarm A binary mode register

Offset: 0x70, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle Fields.

SS

Bits 0-31: Synchronous counter alarm value in Binary mode.

ALRBBINR

RTC alarm B binary mode register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle Fields.

SS

Bits 0-31: Synchronous counter alarm value in Binary mode.

SCB

0xE000ED00: System control block

5/74 fields covered. Toggle Registers.

CPUID

CPUID base register

Offset: 0x0, reset: 0x410FC241, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Implementer
r 		Variant
r 		Constant
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PartNo
r 		Revision
r
Toggle Fields.

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIPENDSET
rw 		PENDSVSET
rw 		PENDSVCLR
rw 		PENDSTSET
rw 		PENDSTCLR
rw 		ISRPENDING
rw 		VECTPENDING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTPENDING
rw 		RETTOBASE
rw 		VECTACTIVE
rw
Toggle Fields.

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBLOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBLOFF
rw
Toggle Fields.

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEYSTAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIANESS
rw 		PRIGROUP
rw 		SYSRESETREQ
rw 		VECTCLRACTIVE
rw 		VECTRESET
rw
Toggle Fields.

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEVEONPEND
rw 		SLEEPDEEP
rw 		SLEEPONEXIT
rw
Toggle Fields.

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKALIGN
rw 		BFHFNMIGN
rw 		DIV_0_TRP
rw 		UNALIGN__TRP
rw 		USERSETMPEND
rw 		NONBASETHRDENA
rw
Toggle Fields.

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_5
rw 		PRI_4
rw
Toggle Fields.

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_15
rw 		PRI_14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCSR

System handler control and state register

Offset: 0x24, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USGFAULTENA
rw 		BUSFAULTENA
rw 		MEMFAULTENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVCALLPENDED
rw 		BUSFAULTPENDED
rw 		MEMFAULTPENDED
rw 		USGFAULTPENDED
rw 		SYSTICKACT
rw 		PENDSVACT
rw 		MONITORACT
rw 		SVCALLACT
rw 		USGFAULTACT
rw 		BUSFAULTACT
rw 		MEMFAULTACT
rw
Toggle Fields.

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVBYZERO
rw 		UNALIGNED
rw 		NOCP
rw 		INVPC
rw 		INVSTATE
rw 		UNDEFINSTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFARVALID
rw 		LSPERR
rw 		STKERR
rw 		UNSTKERR
rw 		IMPRECISERR
rw 		PRECISERR
rw 		IBUSERR
rw 		MMARVALID
rw 		MLSPERR
rw 		MSTKERR
rw 		MUNSTKERR
rw 		IACCVIOL
rw
Toggle Fields.

IACCVIOL

Bit 1: Instruction access violation flag.

MUNSTKERR

Bit 3: Memory manager fault on unstacking for a return from exception.

MSTKERR

Bit 4: Memory manager fault on stacking for exception entry..

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: Memory Management Fault Address Register (MMAR) valid flag.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUG_VT
rw 		FORCED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTTBL
rw
Toggle Fields.

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMFAR
rw
Toggle Fields.

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFAR
rw
Toggle Fields.

BFAR

Bits 0-31: Bus fault address.

AFSR

Auxiliary fault status register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMPDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMPDEF
rw
Toggle Fields.

IMPDEF

Bits 0-31: Implementation defined.

SCB_ACTRL

0xE000E008: System control block ACTLR

0/5 fields covered. Toggle Registers.

ACTRL

Auxiliary control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISOOFP
rw 		DISFPCA
rw 		DISFOLD
rw 		DISDEFWBUF
rw 		DISMCYCINT
rw
Toggle Fields.

DISMCYCINT

Bit 0: DISMCYCINT.

DISDEFWBUF

Bit 1: DISDEFWBUF.

DISFOLD

Bit 2: DISFOLD.

DISFPCA

Bit 8: DISFPCA.

DISOOFP

Bit 9: DISOOFP.

SPI1

0x40013000: Serial peripheral interface/Inter-IC sound

12/53 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

10/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: CHSIDE.

UDR

Bit 3: UDR.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASTRTEN
rw 		I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: CHLEN.

DATLEN

Bits 1-2: DATLEN.

CKPOL

Bit 3: CKPOL.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

I2SCFG

Bits 8-9: I2SCFG.

I2SE

Bit 10: I2SE.

I2SMOD

Bit 11: I2SMOD.

ASTRTEN

Bit 12: ASTRTEN.

I2SPR

prescaler register

Offset: 0x20, reset: 0x00000002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2SDIV.

ODD

Bit 8: ODD.

MCKOE

Bit 9: MCKOE.

SPI2

0x40003800: Serial peripheral interface/Inter-IC sound

12/53 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

10/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: CHSIDE.

UDR

Bit 3: UDR.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASTRTEN
rw 		I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: CHLEN.

DATLEN

Bits 1-2: DATLEN.

CKPOL

Bit 3: CKPOL.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

I2SCFG

Bits 8-9: I2SCFG.

I2SE

Bit 10: I2SE.

I2SMOD

Bit 11: I2SMOD.

ASTRTEN

Bit 12: ASTRTEN.

I2SPR

prescaler register

Offset: 0x20, reset: 0x00000002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2SDIV.

ODD

Bit 8: ODD.

MCKOE

Bit 9: MCKOE.

SPI3

0x58010000: Serial peripheral interface/Inter-IC sound

12/53 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

10/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: CHSIDE.

UDR

Bit 3: UDR.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASTRTEN
rw 		I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: CHLEN.

DATLEN

Bits 1-2: DATLEN.

CKPOL

Bit 3: CKPOL.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

I2SCFG

Bits 8-9: I2SCFG.

I2SE

Bit 10: I2SE.

I2SMOD

Bit 11: I2SMOD.

ASTRTEN

Bit 12: ASTRTEN.

I2SPR

prescaler register

Offset: 0x20, reset: 0x00000002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2SDIV.

ODD

Bit 8: ODD.

MCKOE

Bit 9: MCKOE.

STK

0xE000E010: SysTick timer

0/9 fields covered. Toggle Registers.

CTRL

SysTick control and status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNTFLAG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSOURCE
rw 		TICKINT
rw 		ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD

SysTick reload value register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOAD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle Fields.

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT
rw
Toggle Fields.

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOREF
rw 		SKEW
rw 		TENMS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TENMS
rw
Toggle Fields.

TENMS

Bits 0-23: Calibration value.

SKEW

Bit 30: SKEW flag: Indicates whether the TENMS value is exact.

NOREF

Bit 31: NOREF flag. Reads as zero.

SYSCFG

0x40010000: System configuration controller

2/126 fields covered. Toggle Registers.

MEMRMP

memory remap register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM_MODE
rw
Toggle Fields.

MEM_MODE

Bits 0-2: Memory mapping selection.

CFGR1

configuration register 1

Offset: 0x4, reset: 0x7C000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C3_FMP
rw 		I2C2_FMP
rw 		I2C1_FMP
rw 		I2C_PB9_FMP
rw 		I2C_PB8_FMP
rw 		I2C_PB7_FMP
rw 		I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOSTEN
rw
Toggle Fields.

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C2_FMP

Bit 21: I2C2 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw 		EXTI2
rw 		EXTI1
rw 		EXTI0
rw
Toggle Fields.

EXTI0

Bits 0-2: EXTI 0 configuration bits.

EXTI1

Bits 4-6: EXTI 1 configuration bits.

EXTI2

Bits 8-10: EXTI 2 configuration bits.

EXTI3

Bits 12-14: EXTI 3 configuration bits.

EXTICR2

external interrupt configuration register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw 		EXTI6
rw 		EXTI5
rw 		EXTI4
rw
Toggle Fields.

EXTI4

Bits 0-2: EXTI 4 configuration bits.

EXTI5

Bits 4-6: EXTI 5 configuration bits.

EXTI6

Bits 8-10: EXTI 6 configuration bits.

EXTI7

Bits 12-14: EXTI 7 configuration bits.

EXTICR3

external interrupt configuration register 3

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw 		EXTI10
rw 		EXTI9
rw 		EXTI8
rw
Toggle Fields.

EXTI8

Bits 0-2: EXTI 8 configuration bits.

EXTI9

Bits 4-6: EXTI 9 configuration bits.

EXTI10

Bits 8-10: EXTI 10 configuration bits.

EXTI11

Bits 12-14: EXTI 11 configuration bits.

EXTICR4

external interrupt configuration register 4

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw 		EXTI14
rw 		EXTI13
rw 		EXTI12
rw
Toggle Fields.

EXTI12

Bits 0-2: EXTI12 configuration bits.

EXTI13

Bits 4-6: EXTI13 configuration bits.

EXTI14

Bits 8-10: EXTI14 configuration bits.

EXTI15

Bits 12-14: EXTI15 configuration bits.

SCSR

SCSR

Offset: 0x18, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKASRAMBSY
r 		SRAMBSY
r 		SRAM2ER
rw
Toggle Fields.

SRAM2ER

Bit 0: SRAM2 erase.

SRAMBSY

Bit 1: SRAM1, SRAM2 and PKA SRAM busy by erase operation.

PKASRAMBSY

Bit 8: PKA SRAM busy by erase operation.

CFGR2

CFGR2

Offset: 0x1C, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPF
rw 		ECCL
rw 		PVDL
rw 		SPL
rw 		CLL
rw
Toggle Fields.

CLL

Bit 0: CPU1 LOCKUP (Hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SWPR

SWPR

Offset: 0x20, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31WP
rw 		P30WP
rw 		P29WP
rw 		P28WP
rw 		P27WP
rw 		P26WP
rw 		P25WP
rw 		P24WP
rw 		P23WP
rw 		P22WP
rw 		P21WP
rw 		P20WP
rw 		P19WP
rw 		P18WP
rw 		P17WP
rw 		P16WP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15WP
rw 		P14WP
rw 		P13WP
rw 		P12WP
rw 		P11WP
rw 		P10WP
rw 		P9WP
rw 		P8WP
rw 		P7WP
rw 		P6WP
rw 		P5WP
rw 		P4WP
rw 		P3WP
rw 		P2WP
rw 		P1WP
rw 		P0WP
rw
Toggle Fields.

P0WP

Bit 0: SRAM2 1Kbyte page 0 write protection.

P1WP

Bit 1: SRAM2 1Kbyte page 1 write protection.

P2WP

Bit 2: SRAM2 1Kbyte page 2 write protection.

P3WP

Bit 3: SRAM2 1Kbyte page 3 write protection.

P4WP

Bit 4: SRAM2 1Kbyte page 4 write protection.

P5WP

Bit 5: SRAM2 1Kbyte page 5 write protection.

P6WP

Bit 6: SRAM2 1Kbyte page 6 write protection.

P7WP

Bit 7: SRAM2 1Kbyte page 7 write protection.

P8WP

Bit 8: SRAM2 1Kbyte page 8 write protection.

P9WP

Bit 9: SRAM2 1Kbyte page 9 write protection.

P10WP

Bit 10: SRAM2 1Kbyte page 10 write protection.

P11WP

Bit 11: SRAM2 1Kbyte page 11 write protection.

P12WP

Bit 12: SRAM2 1Kbyte page 12 write protection.

P13WP

Bit 13: SRAM2 1Kbyte page 13 write protection.

P14WP

Bit 14: SRAM2 1Kbyte page 14 write protection.

P15WP

Bit 15: SRAM2 1Kbyte page 15 write protection.

P16WP

Bit 16: SRAM2 1Kbyte page 16 write protection.

P17WP

Bit 17: SRAM2 1Kbyte page 17 write protection.

P18WP

Bit 18: SRAM2 1Kbyte page 18 write protection.

P19WP

Bit 19: SRAM2 1Kbyte page 19 write protection.

P20WP

Bit 20: SRAM2 1Kbyte page 20 write protection.

P21WP

Bit 21: SRAM2 1Kbyte page 21 write protection.

P22WP

Bit 22: SRAM2 1Kbyte page 22 write protection.

P23WP

Bit 23: SRAM2 1Kbyte page 23 write protection.

P24WP

Bit 24: SRAM2 1Kbyte page 24 write protection.

P25WP

Bit 25: SRAM2 1Kbyte page 25 write protection.

P26WP

Bit 26: SRAM2 1Kbyte page 26 write protection.

P27WP

Bit 27: SRAM2 1Kbyte page 27 write protection.

P28WP

Bit 28: SRAM2 1Kbyte page 28 write protection.

P29WP

Bit 29: SRAM2 1Kbyte page 29 write protection.

P30WP

Bit 30: SRAM2 1Kbyte page 30 write protection.

P31WP

Bit 31: SRAM2 1Kbyte page 31 write protection.

SKR

SKR

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-7: SRAM2 write protection key for software erase.

IMR1

SYSCFG CPU1 interrupt mask register 1

Offset: 0x100, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15IM
rw 		EXTI14IM
rw 		EXTI13IM
rw 		EXTI12IM
rw 		EXTI11IM
rw 		EXTI10IM
rw 		EXTI9IM
rw 		EXTI8IM
rw 		EXTI7IM
rw 		EXTI6IM
rw 		EXTI5IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCSSRUIM
rw 		RTCSTAMPTAMPLSECSSIM
rw
Toggle Fields.

RTCSTAMPTAMPLSECSSIM

Bit 0: RTCSTAMPTAMPLSECSSIM.

RTCSSRUIM

Bit 2: RTCSSRUIM.

EXTI5IM

Bit 21: EXTI5IM.

EXTI6IM

Bit 22: EXTI6IM.

EXTI7IM

Bit 23: EXTI7IM.

EXTI8IM

Bit 24: EXTI8IM.

EXTI9IM

Bit 25: EXTI9IM.

EXTI10IM

Bit 26: EXTI10IM.

EXTI11IM

Bit 27: EXTI11IM.

EXTI12IM

Bit 28: EXTI12IM.

EXTI13IM

Bit 29: EXTI13IM.

EXTI14IM

Bit 30: EXTI14IM.

EXTI15IM

Bit 31: EXTI15IM.

IMR2

SYSCFG CPU1 interrupt mask register 2

Offset: 0x104, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PVDIM
rw 		PVM3IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PVM3IM

Bit 18: PVM3IM.

PVDIM

Bit 20: PVDIM.

C2IMR1

SYSCFG CPU2 interrupt mask register 1

Offset: 0x108, reset: 0x00000000, access: read-write

0/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15IM
rw 		EXTI14IM
rw 		EXTI13IM
rw 		EXTI12IM
rw 		EXTI11IM
rw 		EXTI10IM
rw 		EXTI9IM
rw 		EXTI8IM
rw 		EXTI7IM
rw 		EXTI6IM
rw 		EXTI5IM
rw 		EXTI4IM
rw 		EXTI3IM
rw 		EXTI2IM
rw 		EXTI1IM
rw 		EXTI0IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACIM
rw 		ADCIM
rw 		COMPIM
rw 		AESIM
rw 		PKAIM
rw 		FLASHIM
rw 		RCCIM
rw 		RTCWKUPIM
rw 		RTCSSRUIM
rw 		RTCALARMIM
rw 		RTCSTAMPTAMPLSECSSIM
rw
Toggle Fields.

RTCSTAMPTAMPLSECSSIM

Bit 0: RTCSTAMPTAMPLSECSSIM.

RTCALARMIM

Bit 1: RTCALARMIM.

RTCSSRUIM

Bit 2: RTCSSRUIM.

RTCWKUPIM

Bit 3: RTCWKUPIM.

RCCIM

Bit 5: RCCIM.

FLASHIM

Bit 6: FLASHIM.

PKAIM

Bit 8: PKAIM.

AESIM

Bit 10: AESIM.

COMPIM

Bit 11: COMPIM.

ADCIM

Bit 12: ADCIM.

DACIM

Bit 13: DACIM.

EXTI0IM

Bit 16: EXTI0IM.

EXTI1IM

Bit 17: EXTI1IM.

EXTI2IM

Bit 18: EXTI2IM.

EXTI3IM

Bit 19: EXTI3IM.

EXTI4IM

Bit 20: EXTI4IM.

EXTI5IM

Bit 21: EXTI5IM.

EXTI6IM

Bit 22: EXTI6IM.

EXTI7IM

Bit 23: EXTI7IM.

EXTI8IM

Bit 24: EXTI8IM.

EXTI9IM

Bit 25: EXTI9IM.

EXTI10IM

Bit 26: EXTI10IM.

EXTI11IM

Bit 27: EXTI11IM.

EXTI12IM

Bit 28: EXTI12IM.

EXTI13IM

Bit 29: EXTI13IM.

EXTI14IM

Bit 30: EXTI14IM.

EXTI15IM

Bit 31: EXTI15IM.

C2IMR2

SYSCFG CPU2 interrupt mask register 2

Offset: 0x10C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PVDIM
rw 		PVM3IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAMUX1IM
rw 		DMA2CH7IM
rw 		DMA2CH6IM
rw 		DMA2CH5IM
rw 		DMA2CH4IM
rw 		DMA2CH3IM
rw 		DMA2CH2IM
rw 		DMA2CH1IM
rw 		DMA1CH7IM
rw 		DMA1CH6IM
rw 		DMA1CH5IM
rw 		DMA1CH4IM
rw 		DMA1CH3IM
rw 		DMA1CH2IM
rw 		DMA1CH1IM
rw
Toggle Fields.

DMA1CH1IM

Bit 0: DMA1CH1IM.

DMA1CH2IM

Bit 1: DMA1CH2IM.

DMA1CH3IM

Bit 2: DMA1CH3IM.

DMA1CH4IM

Bit 3: DMA1CH4IM.

DMA1CH5IM

Bit 4: DMA1CH5IM.

DMA1CH6IM

Bit 5: DMA1CH6IM.

DMA1CH7IM

Bit 6: DMA1CH7IM.

DMA2CH1IM

Bit 8: DMA2CH1IM.

DMA2CH2IM

Bit 9: DMA2CH2IM.

DMA2CH3IM

Bit 10: DMA2CH3IM.

DMA2CH4IM

Bit 11: DMA2CH4IM.

DMA2CH5IM

Bit 12: DMA2CH5IM.

DMA2CH6IM

Bit 13: DMA2CH6IM.

DMA2CH7IM

Bit 14: DMA2CH7IM.

DMAMUX1IM

Bit 15: DMAMUX1IM.

PVM3IM

Bit 18: PVM3IM.

PVDIM

Bit 20: PVDIM.

RFDCR

radio debug control register

Offset: 0x208, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFTBSEL
rw
Toggle Fields.

RFTBSEL

Bit 0: radio debug test bus selection.

SYSCFG_continue

0x40010100: System configuration controller

0/59 fields covered. Toggle Registers.

IMR1

IMR1

Offset: 0x0, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15IM
rw 		EXTI14IM
rw 		EXTI13IM
rw 		EXTI12IM
rw 		EXTI11IM
rw 		EXTI10IM
rw 		EXTI9IM
rw 		EXTI8IM
rw 		EXTI7IM
rw 		EXTI6IM
rw 		EXTI5IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCSSRUIM
rw 		RTCSTAMPTAMPLSECSSIM
rw
Toggle Fields.

RTCSTAMPTAMPLSECSSIM

Bit 0: RTCSTAMPTAMPLSECSSIM.

RTCSSRUIM

Bit 2: RTCSSRUIM.

EXTI5IM

Bit 21: Peripheral EXTI5 interrupt mask to CPU1.

EXTI6IM

Bit 22: Peripheral EXTI6 interrupt mask to CPU1.

EXTI7IM

Bit 23: Peripheral EXTI7 interrupt mask to CPU1.

EXTI8IM

Bit 24: Peripheral EXTI8 interrupt mask to CPU1.

EXTI9IM

Bit 25: Peripheral EXTI9 interrupt mask to CPU1.

EXTI10IM

Bit 26: Peripheral EXTI10 interrupt mask to CPU1.

EXTI11IM

Bit 27: Peripheral EXTI11 interrupt mask to CPU1.

EXTI12IM

Bit 28: Peripheral EXTI12 interrupt mask to CPU1.

EXTI13IM

Bit 29: Peripheral EXTI13 interrupt mask to CPU1.

EXTI14IM

Bit 30: Peripheral EXTI14 interrupt mask to CPU1.

EXTI15IM

Bit 31: Peripheral EXTI15 interrupt mask to CPU1.

IMR2

IMR2

Offset: 0x4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PVDIM
rw 		PVM3IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PVM3IM

Bit 18: Peripheral xxx interrupt mask to CPU1.

PVDIM

Bit 20: Peripheral xxx interrupt mask to CPU1.

C2IMR1

C2IMR1

Offset: 0x8, reset: 0x00000000, access: read-write

0/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15IM
rw 		EXTI14IM
rw 		EXTI13IM
rw 		EXTI12IM
rw 		EXTI11IM
rw 		EXTI10IM
rw 		EXTI9IM
rw 		EXTI8IM
rw 		EXTI7IM
rw 		EXTI6IM
rw 		EXTI5IM
rw 		EXTI4IM
rw 		EXTI3IM
rw 		EXTI2IM
rw 		EXTI1IM
rw 		EXTI0IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1IM
rw 		ADCIM
rw 		COMPIM
rw 		AES1IM
rw 		PKAIM
rw 		FLASHIM
rw 		RCCIM
rw 		RTCWKUPIM
rw 		RTCSSRUIM
rw 		RTCALARMIM
rw 		RTCSTAMPTAMPLSECSSIM
rw
Toggle Fields.

RTCSTAMPTAMPLSECSSIM

Bit 0: Peripheral RTCSTAMPTAMPLSECSS interrupt mask to CPU2.

RTCALARMIM

Bit 1: Peripheral RTCALARM interrupt mask to CPU2.

RTCSSRUIM

Bit 2: RTCSSRUIM.

RTCWKUPIM

Bit 3: Peripheral RTCWKUP interrupt mask to CPU2.

RCCIM

Bit 5: Peripheral RCC interrupt mask to CPU2.

FLASHIM

Bit 6: Peripheral FLASH interrupt mask to CPU2.

PKAIM

Bit 8: PKAIM.

AES1IM

Bit 10: AES1IM.

COMPIM

Bit 11: Peripheral COMP interrupt mask to CPU2.

ADCIM

Bit 12: Peripheral ADC interrupt mask to CPU2.

DAC1IM

Bit 13: Peripheral DAC1 interrupt mask to CPU2.

EXTI0IM

Bit 16: Peripheral EXTI0 interrupt mask to CPU2.

EXTI1IM

Bit 17: Peripheral EXTI1 interrupt mask to CPU2.

EXTI2IM

Bit 18: Peripheral EXTI2 interrupt mask to CPU2.

EXTI3IM

Bit 19: Peripheral EXTI3 interrupt mask to CPU2.

EXTI4IM

Bit 20: Peripheral EXTI4 interrupt mask to CPU2.

EXTI5IM

Bit 21: Peripheral EXTI5 interrupt mask to CPU2.

EXTI6IM

Bit 22: Peripheral EXTI6 interrupt mask to CPU2.

EXTI7IM

Bit 23: Peripheral EXTI7 interrupt mask to CPU2.

EXTI8IM

Bit 24: Peripheral EXTI8 interrupt mask to CPU2.

EXTI9IM

Bit 25: Peripheral EXTI9 interrupt mask to CPU2.

EXTI10IM

Bit 26: Peripheral EXTI10 interrupt mask to CPU2.

EXTI11IM

Bit 27: Peripheral EXTI11 interrupt mask to CPU2.

EXTI12IM

Bit 28: Peripheral EXTI12 interrupt mask to CPU2.

EXTI13IM

Bit 29: Peripheral EXTI13 interrupt mask to CPU2.

EXTI14IM

Bit 30: Peripheral EXTI14 interrupt mask to CPU2.

EXTI15IM

Bit 31: Peripheral EXTI15 interrupt mask to CPU2.

C2IMR2

C2IMR2

Offset: 0xC, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PVDIM
rw 		PVM3IM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAMUX1IM
rw 		DMA2CH7IM
rw 		DMA2CH6IM
rw 		DMA2CH5IM
rw 		DMA2CH4IM
rw 		DMA2CH3IM
rw 		DMA2CH2IM
rw 		DMA2CH1IM
rw 		DMA1CH7IM
rw 		DMA1CH6IM
rw 		DMA1CH5IM
rw 		DMA1CH4IM
rw 		DMA1CH3IM
rw 		DMA1CH2IM
rw 		DMA1CH1IM
rw
Toggle Fields.

DMA1CH1IM

Bit 0: Peripheral DMA1CH1 interrupt mask to CPU2.

DMA1CH2IM

Bit 1: Peripheral DMA1CH2 interrupt mask to CPU2.

DMA1CH3IM

Bit 2: Peripheral DMA1CH3 interrupt mask to CPU2.

DMA1CH4IM

Bit 3: Peripheral DMA1CH4 interrupt mask to CPU2.

DMA1CH5IM

Bit 4: Peripheral DMA1CH5 interrupt mask to CPU2.

DMA1CH6IM

Bit 5: Peripheral DMA1CH6 interrupt mask to CPU2.

DMA1CH7IM

Bit 6: Peripheral DMA1CH7 interrupt mask to CPU2.

DMA2CH1IM

Bit 8: Peripheral DMA2CH1 interrupt mask to CPU2.

DMA2CH2IM

Bit 9: Peripheral DMA2CH2 interrupt mask to CPU2.

DMA2CH3IM

Bit 10: Peripheral DMA2CH3 interrupt mask to CPU2.

DMA2CH4IM

Bit 11: Peripheral DMA2CH4 interrupt mask to CPU2.

DMA2CH5IM

Bit 12: Peripheral DMA2CH5 interrupt mask to CPU2.

DMA2CH6IM

Bit 13: Peripheral DMA2CH6 interrupt mask to CPU2.

DMA2CH7IM

Bit 14: Peripheral DMA2CH7 interrupt mask to CPU2.

DMAMUX1IM

Bit 15: Peripheral DMAMUX1 interrupt mask to CPU2.

PVM3IM

Bit 18: Peripheral PVM3 interrupt mask to CPU2.

PVDIM

Bit 20: Peripheral PVD interrupt mask to CPU2.

TAMP

0x4000B000: Tamper and backup registers

15/74 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0xFFFF0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8E
rw 		ITAMP6E
rw 		ITAMP5E
rw 		ITAMP3E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3E
rw 		TAMP2E
rw 		TAMP1E
rw
Toggle Fields.

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

TAMP3E

Bit 2: TAMP2E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP6E

Bit 21: ITAMP6E.

ITAMP8E

Bit 23: ITAMP8E.

CR2

control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP3TRG
rw 		TAMP2TRG
rw 		TAMP1TRG
rw 		BKERASE
rw 		TAMP3MSK
rw 		TAMP2MSK
rw 		TAMP1MSK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3NOER
rw 		TAMP2NOER
rw 		TAMP1NOER
rw
Toggle Fields.

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP3NOER

Bit 2: TAMP3NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP3MSK

Bit 18: TAMP3MSK.

BKERASE

Bit 23: Backup registerserase.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

TAMP3TRG

Bit 26: TAMP3TRG.

CR3

TAMP control register 3

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITAMP8NOER
rw 		ITAMP6NOER
rw 		ITAMP5NOER
rw 		ITAMP3NOER
rw
Toggle Fields.

ITAMP3NOER

Bit 2: ITAMP3NOER.

ITAMP5NOER

Bit 4: ITAMP5NOER.

ITAMP6NOER

Bit 5: ITAMP6NOER.

ITAMP8NOER

Bit 7: ITAMP8NOER.

FLTCR

TAMP filter control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw
Toggle Fields.

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

IER

TAMP interrupt enable register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8IE
rw 		ITAMP6IE
rw 		ITAMP5IE
rw 		ITAMP3IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3IE
rw 		TAMP2IE
rw 		TAMP1IE
rw
Toggle Fields.

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

TAMP3IE

Bit 2: TAMP3IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP6IE

Bit 21: ITAMP6IE.

ITAMP8IE

Bit 23: ITAMP8IE.

SR

TAMP status register

Offset: 0x30, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8F
r 		ITAMP6F
r 		ITAMP5F
r 		ITAMP3F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3F
r 		TAMP2F
r 		TAMP1F
r
Toggle Fields.

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

TAMP3F

Bit 2: TAMP3F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP6F

Bit 21: ITAMP6F.

ITAMP8F

Bit 23: ITAMP8F.

MISR

TAMP masked interrupt status register

Offset: 0x34, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r 		ITAMP6MF
r 		ITAMP5MF
r 		ITAMP3MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3MF
r 		TAMP2MF
r 		TAMP1MF
r
Toggle Fields.

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP6MF

Bit 21: ITAMP6MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SCR

TAMP status clear register

Offset: 0x3C, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CITAMP8F
w 		CITAMP6F
w 		CITAMP5F
w 		CITAMP3F
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP3F
w 		CTAMP2F
w 		CTAMP1F
w
Toggle Fields.

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CTAMP3F

Bit 2: CTAMP3F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP6F

Bit 21: CITAMP6F.

CITAMP8F

Bit 23: CITAMP8F.

COUNTR

monotonic counter register

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle Fields.

COUNT

Bits 0-31: COUNT.

BKP0R

TAMP backup register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP1R

TAMP backup register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP2R

TAMP backup register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP3R

TAMP backup register

Offset: 0x10C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP4R

TAMP backup register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP5R

TAMP backup register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP6R

TAMP backup register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP7R

TAMP backup register

Offset: 0x11C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP8R

TAMP backup register

Offset: 0x120, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP9R

TAMP backup register

Offset: 0x124, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP10R

TAMP backup register

Offset: 0x140, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP11R

TAMP backup register

Offset: 0x144, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP12R

TAMP backup register

Offset: 0x148, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP13R

TAMP backup register

Offset: 0x14C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP14R

TAMP backup register

Offset: 0x150, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP15R

TAMP backup register

Offset: 0x154, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP16R

TAMP backup register

Offset: 0x158, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP17R

TAMP backup register

Offset: 0x15C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP18R

TAMP backup register

Offset: 0x160, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

BKP19R

TAMP backup register

Offset: 0x164, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

TIM1

0x40012C00: Advanced-control timers

1/190 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1 (OC1 output).

OIS1N

Bit 9: Output Idle state 1 (OC1N output).

OIS2

Bit 10: Output Idle state 2 (OC2 output).

OIS2N

Bit 11: Output Idle state 2 (OC2N output).

OIS3

Bit 12: Output Idle state 3 (OC3 output).

OIS3N

Bit 13: Output Idle state 3 (OC3N output).

OIS4

Bit 14: Output Idle state 4 (OC4 output).

OIS5

Bit 16: Output Idle state 5 (OC5 output).

OIS6

Bit 18: Output Idle state 6 (OC6 output).

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS3_4
rw 		SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection.

TS3_4

Bits 20-21: Trigger selection.

DIER

DMA/interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/Compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COM
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle Fields.

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/Compare 1 generation.

CC2G

Bit 2: Capture/Compare 2 generation.

CC3G

Bit 3: Capture/Compare 3 generation.

CC4G

Bit 4: Capture/Compare 4 generation.

COM

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle Fields.

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0xFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-15: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle Fields.

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle Fields.

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle Fields.

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DT
rw
Toggle Fields.

DT

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

option register 1

Offset: 0x50, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw 		TIM1_ETR_ADC1_RMP
rw
Toggle Fields.

TIM1_ETR_ADC1_RMP

Bits 0-1: TIM1_ETR_ADC1 remapping capability.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3OutputComparemode

capture/compare mode register 3

Offset: 0x54, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M_3
rw 		OC5M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle Fields.

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M_3

Bit 16: OC5M.

OC6M_3

Bit 24: OC6M.

CCR5

capture/compare register 5

Offset: 0x58, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle Fields.

CCR5

Bits 0-15: Capture/Compare 5 value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 6

Offset: 0x5C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle Fields.

CCR6

Bits 0-15: Capture/Compare 6 value.

AF1

alternate function option register 1

Offset: 0x60, reset: 0x00000001, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ResETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ResETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ResETRSEL

Bits 14-17: ETR source selection.

AF2

Alternate function register 2

Offset: 0x64, reset: 0x00000001, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle Fields.

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2INP

Bit 9: BRK2 BKIN2 input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TISEL

timer input selection register

Offset: 0x68, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw 		TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input.

TI3SEL

Bits 16-19: selects TI3[0] to TI3[15] input.

TI4SEL

Bits 24-27: selects TI4[0] to TI4[15] input.

TIM16

0x40014400: General-purpose timers

1/68 fields covered. Toggle Registers.

CR1

TIM16/TIM17 control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

TIM16/TIM17 control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle Fields.

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

DIER

TIM16/TIM17 DMA/interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

TIM16/TIM17 status register

Offset: 0x10, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

TIM16/TIM17 event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC1G
w 		UG
w
Toggle Fields.

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/Compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

TIM16/TIM17 capture/compare mode register 1

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CCER

TIM16/TIM17 capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity.

CNT

TIM16/TIM17 counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPYorRes
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: CNT.

UIFCPYorRes

Bit 31: UIF Copy.

PSC

TIM16/TIM17 prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

TIM16/TIM17 auto-reload register

Offset: 0x2C, reset: 0xFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

TIM16/TIM17 repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

TIM16/TIM17 capture/compare register 1

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

TIM16/TIM17 break and dead-time register

Offset: 0x44, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DT
rw
Toggle Fields.

DT

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

TIM16/TIM17 DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

TIM16/TIM17 DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM16_OR1

TIM16 option register 1

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle Fields.

TI1_RMP

Bits 0-1: Timer 17 input 1 connection.

TIM16_AF1

TIM16 alternate function register 1

Offset: 0x60, reset: 0x00000001, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

TIM16_TISEL

TIM16 input selection register

Offset: 0x68, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TISEL
rw
Toggle Fields.

TISEL

Bits 0-3: TISEL.

TIM17

0x40014800: General-purpose timers

1/68 fields covered. Toggle Registers.

CR1

TIM16/TIM17 control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

TIM16/TIM17 control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle Fields.

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

DIER

TIM16/TIM17 DMA/interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

TIM16/TIM17 status register

Offset: 0x10, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

TIM16/TIM17 event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC1G
w 		UG
w
Toggle Fields.

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/Compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

TIM16/TIM17 capture/compare mode register 1

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CCER

TIM16/TIM17 capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity.

CNT

TIM16/TIM17 counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPYorRes
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: CNT.

UIFCPYorRes

Bit 31: UIF Copy.

PSC

TIM16/TIM17 prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

TIM16/TIM17 auto-reload register

Offset: 0x2C, reset: 0xFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

TIM16/TIM17 repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

TIM16/TIM17 capture/compare register 1

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

TIM16/TIM17 break and dead-time register

Offset: 0x44, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DT
rw
Toggle Fields.

DT

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

TIM16/TIM17 DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

TIM16/TIM17 DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM17_OR1

TIM17 option register 1

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle Fields.

TI1_RMP

Bits 0-1: Timer 17 input 1 connection.

TIM17_AF1

TIM17 alternate function register 1

Offset: 0x60, reset: 0x00000001, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

TIM17_TISEL

TIM17 input selection register

Offset: 0x68, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TISEL
rw
Toggle Fields.

TISEL

Bits 0-3: TISEL.

TIM2

0x40000000: General-purpose-timers

0/117 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle Fields.

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle Fields.

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-31: High counter value (TIM2 only).

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle Fields.

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle Fields.

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle Fields.

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle Fields.

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle Fields.

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM2_OR1

TIM2 option register

Offset: 0x50, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw 		ETR_RMP
rw
Toggle Fields.

ETR_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input capture 4 remap.

TIM2_AF1

TIM2 alternate function option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle Fields.

ETRSEL

Bits 14-17: External trigger source selection.

TIM2_TISEL

TIM2 timer input selection register

Offset: 0x68, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: TI1SEL.

TI2SEL

Bits 8-11: TI2SEL.

TZIC

0x58004800: TrustZone Interrupt Control

14/42 fields covered. Toggle Registers.

IER1

TZIC interrupt enable register 1

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAIE
rw 		SRAM2IE
rw 		SRAM1IE
rw 		FLASHIE
rw 		DMAMUX1IE
rw 		DMA2IE
rw 		DMA1IE
rw 		FLASHIFIE
rw 		PWRIE
rw 		SUBGHZSPIIE
rw 		RNGIE
rw 		AESIE
rw 		TZSCIE
rw 		TZICIE
rw
Toggle Fields.

TZICIE

Bit 0: TZICIE.

TZSCIE

Bit 1: TZSCIE.

AESIE

Bit 2: AESIE.

RNGIE

Bit 3: RNGIE.

SUBGHZSPIIE

Bit 4: SUBGHZSPIIE.

PWRIE

Bit 5: PWRIE.

FLASHIFIE

Bit 6: FLASHIFIE.

DMA1IE

Bit 7: DMA1IE.

DMA2IE

Bit 8: DMA2IE.

DMAMUX1IE

Bit 9: DMAMUX1IE.

FLASHIE

Bit 10: FLASHIE.

SRAM1IE

Bit 11: SRAM1IE.

SRAM2IE

Bit 12: SRAM2IE.

PKAIE

Bit 13: PKAIE.

MISR1

TZIC status register 1

Offset: 0x10, reset: 0x00000000, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAMF
r 		SRAM2MF
r 		SRAM1MF
r 		FLASHMF
r 		DMAMUX1MF
r 		DMA2MF
r 		DMA1MF
r 		FLASHIFMF
r 		PWRMF
r 		SUBGHZSPIMF
r 		RNGMF
r 		AESMF
r 		TZSCMF
r 		TZICMF
r
Toggle Fields.

TZICMF

Bit 0: TZICMF.

TZSCMF

Bit 1: TZSCMF.

AESMF

Bit 2: AESMF.

RNGMF

Bit 3: RNGMF.

SUBGHZSPIMF

Bit 4: SUBGHZSPIMF.

PWRMF

Bit 5: PWRMF.

FLASHIFMF

Bit 6: FLASHIFMF.

DMA1MF

Bit 7: DMA1MF.

DMA2MF

Bit 8: DMA2MF.

DMAMUX1MF

Bit 9: DMAMUX1MF.

FLASHMF

Bit 10: FLASHMF.

SRAM1MF

Bit 11: SRAM1MF.

SRAM2MF

Bit 12: SRAM2MF.

PKAMF

Bit 13: PKAMF.

ICR1

TZIC interrupt status clear register 1

Offset: 0x20, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKACF
rw 		SRAM2CF
rw 		SRAM1CF
rw 		FLASHCF
rw 		DMAMUX1CF
rw 		DMA2CF
rw 		DMA1CF
rw 		FLASHIFCF
rw 		PWRCF
rw 		SUBGHZSPICF
rw 		RNGCF
rw 		AESCF
rw 		TZSCCF
rw 		TZICCF
rw
Toggle Fields.

TZICCF

Bit 0: TZICCF.

TZSCCF

Bit 1: TZSCCF.

AESCF

Bit 2: AESCF.

RNGCF

Bit 3: RNGCF.

SUBGHZSPICF

Bit 4: SUBGHZSPICF.

PWRCF

Bit 5: PWRCF.

FLASHIFCF

Bit 6: FLASHIFCF.

DMA1CF

Bit 7: DMA1CF.

DMA2CF

Bit 8: DMA2CF.

DMAMUX1CF

Bit 9: DMAMUX1CF.

FLASHCF

Bit 10: FLASHCF.

SRAM1CF

Bit 11: SRAM1CF.

SRAM2CF

Bit 12: SRAM2CF.

PKACF

Bit 13: PKACF.

TZSC

0x58004400: Global TrustZone Controller

0/12 fields covered. Toggle Registers.

TZSC_CR

TZSC control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle Fields.

LCK

Bit 0: LCK.

TZSC_SECCFGR1

TZSC security configuration register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKASEC
rw 		RNGSEC
rw 		AESSEC
rw
Toggle Fields.

AESSEC

Bit 2: AESSEC.

RNGSEC

Bit 3: RNGSEC.

PKASEC

Bit 13: PKASEC.

TZSC_PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAPRIV
rw 		SUBGHZSPIPRIV
rw 		RNGPRIV
rw 		AESPRIV
rw
Toggle Fields.

AESPRIV

Bit 2: AESPRIV.

RNGPRIV

Bit 3: RNGPRIV.

SUBGHZSPIPRIV

Bit 4: SUBGHZSPIPRIV.

PKAPRIV

Bit 13: PKAPRIV.

TZSC_MPCWM1_UPWMR

Unprivileged Water Mark 1 register

Offset: 0x130, reset: 0x0FFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

LGTH

Bits 16-27: LGTH.

TZSC_MPCWM1_UPWWMR

Unprivileged Writable Water Mark 1 register

Offset: 0x134, reset: 0x0FFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

LGTH

Bits 16-27: Define the length of Flash Unprivileged Writable area, in 2.

TZSC_MPCWM2_UPWMR

Unprivileged Water Mark 2 register

Offset: 0x138, reset: 0x0FFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

LGTH

Bits 16-27: LGTH.

TZSC_MPCWM3_UPWMR

Unprivileged Water Mark 3 register

Offset: 0x140, reset: 0x0FFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

LGTH

Bits 16-27: LGTH.

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

29/134 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields.

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in low-power mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: Receive data register not empty/RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: Transmit data register empty/TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable deassertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD7_4
rw 		ADD3_0
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: stop bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD3_0

Bits 24-27: Address of the USART node.

ADD7_4

Bits 28-31: Address of the USART node.

CR3

control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT2_0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: OVRDIS: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT2_0

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable.

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: BRR.

GTPR

guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

request register

Offset: 0x18, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
rw 		RXFRQ
rw 		MMRQ
rw 		SBKRQ
rw 		ABRRQ
rw
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

interrupt and status register

Offset: 0x1C, reset: 0x0000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from low-power mode clear flag.

RDR

receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

29/134 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle Fields.

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in low-power mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: Receive data register not empty/RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: Transmit data register empty/TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable deassertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD7_4
rw 		ADD3_0
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: stop bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD3_0

Bits 24-27: Address of the USART node.

ADD7_4

Bits 28-31: Address of the USART node.

CR3

control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT2_0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: OVRDIS: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT2_0

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable.

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: BRR.

GTPR

guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

request register

Offset: 0x18, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
rw 		RXFRQ
rw 		MMRQ
rw 		SBKRQ
rw 		ABRRQ
rw
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

interrupt and status register

Offset: 0x1C, reset: 0x0000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NECF
w 		FECF
w 		PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from low-power mode clear flag.

RDR

receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler.

VREFBUF

0x40010030: Voltage reference buffer

1/5 fields covered. Toggle Registers.

CSR

control and status register

Offset: 0x0, reset: 0x00000002, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r 		VRS
rw 		HIZ
rw 		ENVR
rw
Toggle Fields.

ENVR

Bit 0: Voltage reference buffer mode enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle Fields.

TRIM

Bits 0-5: Trimming code.

WWDG

0x40002C00: System window watchdog

0/6 fields covered. Toggle Registers.

CR

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle Fields.

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, reset: 0x0000007F, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTB
rw 		EWI
w 		W
rw
Toggle Fields.

W

Bits 0-6: 7-bit window value.

EWI

Bit 9: Early wakeup interrupt.

WDGTB

Bits 11-13: Timer base.

SR

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.